Submitted to CICC 2005 1Abstract This paper presents the opportunities and challenges for scaling A/D converters into ultra-deep-submicron CMOS technologies. With faster transistors and better matching, the trend is to migrate into higher sample rates with lower resolutions. Limited dynamic range at low supply voltages remains the utmost challenge for high-resolution Nyquist converters, and oversampling will become the dominant technique in this arena in the future. Linearity correction with digital calibration is also becoming prevalent as the efficiency of calibration circuitry improves. Introduction Explosive growth in wireless and wireline communications is the dominant driver for higher specifications of analog-to-digital converters (ADCs). New applications in wireless communications support multi-mode operation, utilize large portions of bandwidth, such as in the case of ultra-wideband and 60-GHz-band systems, or attempt to re-use the already licensed spectrum, thus requiring a high dynamic range for operation. Similarly, future wireline communication systems commonly extend the signal constellations to increase the data throughput, such as in the case of 10-Gb/s Ethernet or next-generation cable modems. These applications are driving the demand for high-resolution, high-speed, low power, and low cost integrated ADCs. Technology scaling significantly lowers the cost of digital logic and memory, and there is a great incentive to implement high-volume baseband signal processing in the most advanced process technology available. Concurrently, there is an increased interest in using transistors with minimum channel length and minimum oxide thickness to implement analog functions, because the improved device transition frequency, fT, allows for faster operation. However, scaling adversely affects most other parameters relevant to analog designs. To achieve a high linearity, high sampling speed, high dynamic range, with low supply voltages and low power dissipation in ultra-deep-submicron CMOS technology is a major challenge. In this paper we explore the challenges for ADC design associated with technology scaling. We will examine some circuit, architectural and system design techniques that will allow analog-to-digital converters to utilize transistors available in sub-100-nm technologies. Technology Divergence with Scaling Technology scaling doubles the density of digital logic every 2-3 years. Digital circuits have additionally benefited from scaling through increased operating frequencies and lower power consumption. Scaling to 90-nm CMOS technology and beyond is characterized by limited power. To minimize the dissipation, by balancing the switching and leakage power, digital systems choose the appropriate supply voltages and transistor types. Current foundry offerings are characterized by several thin-oxide devices, with different implant-controlled thresholds, and supply voltages that are scaled below the reliability-dictated levels. Furthermore, the same process usually offers thick-oxide I/O devices. Analog functions can be implemented using either thin- or thick-oxide devices – the thick-oxide devices enjoy the benefit of a larger dynamic range (DR) and the thin-oxide devices harvest a higher operation frequency. This trend will continue in the future as predicted by ITRS (Fig. 1) [87]. Recent requirements to control the digital circuit leakage have slowed down the transistor threshold scaling, with a consequent reduction in supply voltage scaling. As a result, fast analog circuits can use 1V or higher supplies in the next few technology nodes. With continued scaling and the reduction of supply voltages in sub-1V range, the I/O devices will follow to sub-1.8V levels, and analog functions that require a high dynamic range would have to use additional process features or would have to be implemented on a separate chip. 00.511.522.533.5050100150200250Technology node [nm]Supply, Threshold Voltages [V] Precision Analog VDD Digital VDD Threshold Voltages Fig. 1. Scaling of supply and threshold voltages. Scaling of Analog-to-Digital Converters into Ultra-Deep-Submicron CMOS Y. Chiu 1, B. Nikoliü 2, and P. R. Gray 2 1 Electrical and Computer Engineering, University of Illinois at Urbana-Champaign 2 Electrical Engineering and Computer Sciences, University of California at Berkeley 10-1-1IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE0-7803-9023-7/05/$20.00 ©2005 IEEE. 375Submitted to CICC 2005 2Opportunities and Challenges in Scaling Analog Designs As technology advances, there is an increased incentive for high-speed analog designs to exploit higher fT of scaled transistors. A number of challenges presented by technology scaling however must be addressed. Reduced Signal-to-Noise Ratio (SNR). The most prominent challenge for implementing precision analog circuitry in deeply scaled, “digital” processes is the reduction of supply voltages. It lowers the available voltage swings in analog circuits, fundamentally limiting the achievable SNR. To maintain the same dynamic range with a lower supply voltage in a noise-limited design, the circuit noise must also be proportionally reduced. For example, lowering the noise floor in switched-capacitor circuits requires an increase in the capacitor sizes to lower the kT/C noise, hence results in a penalty in power consumption. Lower intrinsic gain. The intrinsic voltage gain (gmro) of an MOS device is one important gauge of device performance for precision analog designs. As scaling continues, the intrinsic gain keeps decreasing due to a lower output resistance as a result of drain-induced barrier lowering (DIBL) and hot carrier impact ionization. In addition, gate leakage currents in very thin-oxide devices will set an upper bound on the attainable effective output resistance via circuit techniques (such as active cascode). Device leakage. A fundamental advantage of MOS technology is the high quality switch naturally available. As scaling continues, the elevated drain-to-source leakage in an off-switch can adversely affect the switch performance. If the switch is driven by an amplifier, the leakage may lower the output resistance of the amplifier, hence limits its low-frequency gain. Charge storage on capacitive devices will become difficult with leaky transistors attached. In addition, the gate leakage current also violates the high-impedance “summing-node” assumption that underlines the operation of