Lab 2: VHDL SimulationCSE 143 MICROELECTRONICS DESIGN, WINTER 2008, PROF. RAJESH GUPTA Lab 2: VHDL Simulation Due: 02/19/2008 noon In this second lab, you will try to optimize a modified version of your design from Lab #1 for the best area/time performance. 1. The first part of the lab will explore how the synthesizer picks different library cells for different timing constraints. You will synthesize a simple adder and multiplier (download the Adder.vhd and Mult.vhd from lab website) with different timing constraints and make a table of the different output areas. You will also need to identify which actual adder and multiplier was used during the synthesis process. • Website with name listings of different adders, mults: http://www.synopsys.com/products/designware/docs/doc/dwf/datasheets/dw01_add.pdfhttp://www.synopsys.com/products/designware/docs/doc/dwf/datasheets/dw02_mult.pdf • Since this is not a clocked design you have to use the set_max_delay command, give it a value in ns (something high initially to make sure you get the slowest library object). You also need to constrain which path it takes so you can use the –from –to fields o Exp. set_max_delay 100 –from A –to C • When you actually compile be sure to use the –map_effort high to get a good area output • To see if your constraints (in this case the max_delay) were met use the report_constraint command • To list the resources used, you can use the report_resources command Receivables: Make a table showing at least three different adder implementations and one multiplier implementations and their corresponding max delays and areas. Name each of the three different implementations with the descriptive name from the website listed above. Also, submit your synthesis scripts, or a transcript of what you typed into the dc_shell-t. 2. For the second part of the lab you will implement the modified algorithm The modified algorithm you will create is: First Round Other Rounds (Rounds 2 – 20) A = initialA + A A = A + A/2 (THIS IS INTEGER DIVISION) B = initialB + B B = B + B/2 (THIS IS INTEGER DIVISION) C = 6*A + B C = 6*A + B Your inputs will be initialA and initialB, your goal is to output the value C after 20 iterations of processing. Your VHDL design must have the following input/output port scheme: CSE 143, Winter 2008, Lab 2 Page 1 of 3Port Name: Type: Size: start input 1 bit clk input 1 bit reset_n input 1 bit initialA input 15 downto 0 bits initialB input 15 downto 0 bits ready output 1 bit done output 1 bit finalc output 15 downto 0 bits Your design should have an entity name of: PowerAccumulator Your design should operate as follows: -the clk signal will provide the clocking signal to help you synchronize your design -your design should not complete any work until the start signal goes high indicating that the initialA and initialB inputs are ready and that you may begin processing - The ready output will be used to signal the test bench when your design is ready to accept more inputs. It should be set to high if the design is ready to accept more inputs, and set to low if it can’t accept any inputs at the current time (this will help facilitate proper pipelining if that is what you are using). -when your design has finished processing and a proper answer is being output to the finalc port, then your design should set done to a high value, your design may only output 1 calculated value per done signal per clock cycle (so if you have the results of two answers ready, then the first done cycle the first answer will be displayed, done will stay high and the second cycle the next answer will be displayed). You should only keep done high for one cycle per answer to output. -if at any time your design sees the reset_n input transition to a LOW value, then your design should reset itself to a reset state and stay in the reset state until reset_n is no longer low Lab #2 Receivables: 1. Write a paragraph explaining your design and how it operates and reacts to the different input signals 2. Provide a copy of all VHDL source code (this includes the VHDL module file and the test bench file used to test your design) 3. Provide a copy of the ModelSim transcript file which contains the output remarks for the supplied Test Bench file given on the class website (this will test your design for correctness) CSE 143, Winter 2008, Lab 2 Page 2 of 34. Provide a copy of the Synopsys synthesis script or a transcript of the commands you typed for synthesis, write a paragraph and give a table showing any intermediate synthesis results 5. Provide your final synthesis results – final clock period, final total area, final total number of cycles needed to complete processing (given from the test bench). 6. Provide a copy of the Synopsys area, timing reports (see the website for details on how to do this) 7. Please zip your files and email to [email protected] Lab #2 Grading Criteria: Besides correctness of the design, part of your total Lab #2 score will be determined by how well in relation to your classmates the overall performance-area of your design is. So aim to optimize your design to reduce cycles to get a better performance number. Also, by tweaking your synthesis script you can also lower this number. Performance Area = Area * Throughput (Amortized time per input = average clock cycles * clock period) -this is in the units of (total cell area * seconds per input) Points Breakdown: 10% - You included all work from part #1 of the lab 40% - Your design works correctly 20% - You included all the source files, transcript file, synthesis output, and synthesis results 10% - You included a paragraph on how your design works and any optimizations you considered 20% - How well your performance area was in relation to the class average CSE 143, Winter 2008, Lab 2 Page 3 of