Digital Circuit ImplementationSlide 2Slide 3Slide 4Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Digital Design ProcessSlide 14Slide 15Slide 16Slide 17Slide 18Digital Circuit ImplementationWafers and ChipsIntegrated circuit (IC) chips are manufactured on silicon wafersTransistors are placed on the wafers through a chemical etching processEach wafer is cut into chips (dies)which are then packaged individuallyChip Manufacturing ProcessCOPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVEDIC CostCost of an integrated circuit (IC) can be modeled with three equationsCost per die = (cost per wafer) / ((dies per wafer) * yield)Yield = fraction of dies on a wafer that pass testingDies per wafer  (wafer area) / (die area)Ignores border of the circular wafer that cannot accommodate a rectangular dieYield = 1 / (1 + (defects per area * die area) / 2)2Based on many years of empirical observationsBasic IC Chip TypesLogic circuits may be implemented …on single chip, or using many chips interconnected on a printed circuit board (PCB)Main types of IC chips are:Standard chipsProgrammable Logic Devices (PLD)Custom chipsStandard ChipsSmall number of transistors (< 100)Simple and fixed functionsLogic designer must decide how to interconnect multiple chips for desired functionAgreed upon / standard functionalityPopular in the 1980s – too large in physical size for much industry use now (good for teaching though!)7400 Series TTL Logic ChipsThe 7400 NAND Chip: pin layout Vcc = +5V Gnd 7400 1 2 3 4 5 6 7 14 13 12 11 10 9 8 001491225101336811The equivalent logic layout7400 Series ImplementationImplementing f = x1x2 + x2'x3 using 7400 series ICsV DDx 1 x 2 x 3 f 74047408 7432Why TTL is Only Used For Small SystemsPLDsProgrammable chips – functionality determined by the designerCan even be reprogrammedCan handle more complex functions than standard chips (approx 100 million transistors per PLD)FPGA: Field Programmable Gate ArraysCPLD: Complex Programmable Logic DevicesPAL: Programmable Array LogicPLA: Programmable Logic ArraysThese are used very extensively in industryCustom ChipsProgrammable chips have two major drawbacks:Consume space due to large number of switches for programmabilitySlow  speed also limited by excessive switches (resistance/capacitance)Custom chipsLogic designer builds a custom chipManufactured by a special fabrication facility ($$$!)ASIC: Application Specific Integrated CircuitFast, smallExpensive! And takes time to build and manufactureDigital Design ProcessDesign Loop for Digital HardwareThe basic design loop:Initial design takes creativity and experienceCAD tools are used for simulation and to work out detailsDesign conceptSuccessful design Initial designSimulationDesign correct? RedesignNoYesThe Entire Development ProcessDesign is only one partVerification and testingare also important – thisis called design verificationErrors may not be uncovereduntil after the prototype is madeErrors may not be uncovereduntil after “release”!Pentium bugRequired productDesign specifications Initial designSimulationDesign correct? RedesignImplement prototypeTesting Meets specs?Finished productMinor errors? Make correctionsNoYes NoYes Yes NoSimulation PhaseFunctional simulationTest the circuit to determine if it correctly performs all the functions that are required Timing simulationTest the circuit to determine if it meets the timing requirementsCorrect functionality does not necessarily lead to fast speedThe physical design / layout will affect the timingInherent gate delaysPhysical wiring leaves metal traces that have resistanceCAD ToolsThere are a number of commonly used industry standard CAD toolsCAD = Computer Aided DesignAltera, Cadence, Mentor Graphics, Synopsys, Synplicity, XilinxWe have Altera productsTools are used for multiple purposesSynthesis, timing simulation, functional simulation, layoutCan even download the design onto a PCBCAD Tools vs TheoryWhy learn any theory if the CAD tools do the work?Initial design must be provided by the designerQuality of final design is a function of the quality of the initial designTools implement the theoryDesigners need to understand how the tools work in order to be effective in using themTools have many optionsKnowing which to select requires knowing what they do and how they do