CS 5330 001 Assignment 4 4 Due 11 59pm 11 12 2024 QUESTION 1 10 Consider the following instruction Instruction Interpretation The datapath for the memory instructions and the R type instructions and rd rs1 rs2 Reg rd Reg rs1 AND Reg rs2 a What are the values of control signals generated by the control from the datapath for this instruction b Which resources blocks perform a useful function for this instruction QUESTION 2 12 Consider the following instruction mix R type 24 I type non lw sw 28 Load Store Branch 25 11 10 Jump 2 a What fraction of all instructions use data memory b What fraction of all instructions use instruction memory c What fraction of all instructions use the sign extend d What is the sign extend doing during cycles in which its output is not needed QUESTION 3 10 When silicon chips are fabricated defects in materials e g silicon and manufacturing errors can result in defective circuits A very common defect is for one signal wire to get broken and always register a logical 0 This is often called a stuck at 0 fault a Which instructions fail to operate correctly if the MemToReg wire is stuck at 0 b Which instructions fail to operate correctly if the ALUSrc wire is stuck at 0 QUESTION 4 12 I type instructions like addi or andi are not included in the following datapath described in the class a What additional logic blocks if any are needed to add I type instructions to the CPU shown above Add any necessary logic blocks to the datapath and explain their purpose b List the values of the signals generated by the control unit for addi Explain the reasoning for any don t care control signals QUESTION 5 15 Problems in this question assume that the logic blocks used to implement a processor s datapath have the following latencies I Mem D Mem 250ps Mux ALU Adder Single Gate 5ps Register Read 30ps Register Setup 20ps 25ps 200ps 150ps Sign extend 50ps File 150ps Register Control 50ps Register read is the time needed after the rising clock edge for the new register value to appear on the output This value applies to the PC only Register setup is the amount of time a register s data input must be stable before the rising edge of the clock This value applies to both the PC and Register File a What is the latency of an R type instruction i e how long must the clock period be to ensure that this instruction works correctly b What is the latency of an lw Check your answer carefully Many students place extra muxes on the critical path c What is the latency of an sw Check your answer carefully Many students place extra muxes on the critical path d What is the latency of beq e What is the latency of an arithmetic or logical I type non load store instruction f What is the minimum clock period for this CPU QUESTION 6 10 In this exercise we examine how pipelining affects the clock cycle time of the processor Problems in this exercise assume that individual stages of the datapath have the following latencies Also assume that instructions executed by the processor are broken down as follows a What is the clock cycle time in a pipelined and non pipelined processor b What is the total latency of an lw instruction in a pipelined and non pipelined processor c If we can split one stage of the pipelined datapath into two new stages each with half the latency of the original stage which stage would you split and what is the new clock cycle time of the processor d Assuming there are no stalls or hazards what is the utilization of the data memory e Assuming there are no stalls or hazards what is the utilization of the write register port of the Registers unit QUESTION 7 7 Assume that s0 is initialized to 11 and s1 is initialized to 22 Suppose you executed the code below on a version of the pipeline described in the class that does not handle data hazards What would the final values of registers s2 and s3 be QUESTION 8 12 Identify ALL of the data dependencies in the following code Which dependencies are data hazards that can be resolved by forwarding For each irresolvable data hazard how many pipeline stalls will occur and in which instruction Draw pipeline stage diagram in the form of IF ID EX MEM WB to show stalls s0 s1 5 s2 s0 s1 s3 s0 15 addi add addi 12 15 14 15 100 12 13 15 12 12 15 13 add lw sub add QUESTION 9 12 In the class we have shown how to maximize performance on a pipelined datapath with forwarding hardware to reduce potential stalls following a load instruction Rewrite the following code to minimize performance on this datapath that is reorder the instructions so that this sequence takes the most clock cycles to execute while still obtaining the same result What if the forwarding hardware is not implemented BONUS 20 Consider the fragment of MIPS assembly below lw lw add add add sw beq 3 0 5 4 4 5 7 7 3 8 8 4 10 7 8 6 0 5 10 11 loop sw lw sub bez add sub s5 12 s3 s5 8 s3 s4 s2 s1 s4 label s2 s0 s1 s2 s6 s1 hazard by reordering code Suppose we modify the pipeline so that it has only one memory that handles both instructions and data In this case there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction access data a Draw a pipeline stage diagram to show where the code above will stall b In general is it possible to reduce the number of stalls resulting from this structural SUBMISSION date permitted Yi Zhao 1 Clearly write your answers to the corresponding questions in a WORD or plain text file 2 Submit your answers clearly marked with your name through eLearning by the due 3 Plagiarizing homework answers obtained from the internet or AI chatbots is not 4 No late homework or assignment will be accepted