AR BR Accumulators 1 1 H I N Z V C 7 0 7 15 15 15 0 7 XR PC SP 0 0 0 0 Index Register Program Counter Stack Pointer Condition Code Register Carry Borrow Over ow Zero Negative Interrupt Mask Half Carry from bit 3 Embedded Systems Laboratory Motorola M6800 Microprocessor ACCUMULATOR and MEMORY OPERATIONS MNEM IMMEDIATE OP DIRECT INDEXED OP OP EXTENDED OP INHERENT OP Each register label refers to contents of register ADDRESSING MODES BOOL ARITH OPERATION CONDITION CODES1 1 4 3 2 1B 2 1 Add Accumulators Add with Carry Add And Arithmetic Shift Left Arithmetic Shift Right ASR Bit Test Compare Accumulators Clear Compare Complement 1 s Decimal Adjust A Decrement Exclusive Or Increment Load Accumulator Logical Shift Right Negate Or Inclusive Push Data Pull Data Rotate Left Rotate Right Subtract Accumulators SBA Subtract with Carry Store Accumulator Subtract Transfer Accumulator Test Value ABA ADCA ADCB ADDA ADDB ANDA ANDB ASL ASLA ASLB ASRA ASRB BITA BITB CBA CLR CLRA CLRB CMPA CMPB COM COMA COMB DAA DEC DECA DECB EORA EORB INC INCA INCB LDAA LDAB LSR LSRA LSRB NEG NEGA NEGB ORAA ORAB PSHA PSHB PULA PULB ROL ROLA ROLB ROR RORA RORB SBCA SBCB STAA STAB SUBA SUBB TAB TBA TST TSTA TSTB 89 C9 8B CB 84 C4 85 C5 81 C1 88 C8 86 C6 8A CA 82 C2 80 C0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 99 D9 9B DB 94 D4 95 D5 91 D1 98 D8 96 D6 9A DA 92 D2 97 D7 90 D0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A9 E9 AB EB A4 E4 68 67 A5 E5 6F A1 E1 63 6A A8 E8 6C A6 E6 64 60 AA EA 69 66 A2 E2 A7 E7 A0 E0 5 5 5 5 5 5 7 7 5 5 7 5 5 7 7 5 5 7 5 5 7 7 5 5 7 7 5 5 6 6 5 5 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 B9 F9 BB FB B4 F4 78 77 B5 F5 7F B1 F1 73 7A B8 F8 7C B6 F6 74 70 BA FA 79 76 B2 F2 B7 F7 B0 F0 4 4 4 4 4 4 6 6 4 4 6 4 4 6 6 4 4 6 4 4 6 6 4 4 6 6 4 4 5 5 4 4 6 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 48 58 47 57 11 4F 5F 43 53 19 4A 5A 4C 5C 44 54 40 50 36 37 32 33 49 59 46 56 10 16 17 4D 5D 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 2 2 2 2 2 2 2 2 2 cid 27 cid 27 0 b0 b0 C A B A A M C A B M C B A M A B M B A M A B M B cid 27 C b7 b7 A M B M A B 00 M 00 A 00 B A M B M M M A A B B Convert Binary Addition of BCD M 1 M A 1 A B 1 B A M A B M B M 1 M A 1 A B 1 B M A M B 0 b7 b0 C 00 M M 00 A A 00 B B A M A B M B A MSP SP 1 SP B MSP SP 1 SP SP 1 SP MSP A SP 1 SP MSP B cid 27 cid 27 C b7 b0 cid 27 b0 C b7 A B A A M C A B M C B A M B M A M A B M B A B B A M 00 A 00 B 00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 H l l l l l I N l l l l l l l l l l l l l l l l R R R l l l l l l l l l l l l l l l l R R R l l l l l l l l l l l l l l l l l l l l l l l Z l l l l l l l l l l l l l l l l S S S l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l V l l l l l R R 2 2 2 2 2 2 R R l R R R l l R R R l l l l R R l l l R R 2 2 2 l l l R R 2 2 2 2 2 2 l l l R R l l R R R R R 0 C l l l l l l l l l l l l R R R l l S S S 3 l l l l l l l l l l l l l l l l l R R R 6D 2 7D Copyright c cid 13 2002 2003 by David C Pheanis all rights reserved January 15 2003 XR and SP OPERATIONS MNEM IMMEDIATE DIRECT INDEXED OP OP EXTENDED OP INHERENT OP Each register label refers to contents of register OP 8C 3 3 9C 4 2 AC 6 2 BC 5 3 ADDRESSING MODES BOOL ARITH OPERATION CONDITION CODES1 1 4 3 2 8E CE 3 3 3 3 AE EE AF EF 6 6 7 7 2 2 2 2 BE FE BF FF 5 5 6 6 3 3 3 3 34 09 31 08 30 35 4 4 4 4 4 4 1 1 1 1 1 1 XMS M XLS M 1 SP 1 SP X 1 X SP 1 SP X 1 X M SPMS M 1 SPLS M XMS M 1 XLS SPMS M SPLS M 1 XMS M XLS M 1 SP 1 X X 1 SP MNEM RELATIVE INDEXED OP OP EXTENDED OP …
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