The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL Comp 411 Computer Organization Fall 2015 Prof Montek Singh Final Exam SAMPLE QUESTIONS The actual exam will have 20 25 questions Note These questions do not cover all of the material that is covered on the final exam Please use these only as guidance for the type of questions you can expect on the actual exam 1 3 points Show the transistor level diagram of a single CMOS logic gate A B C F that implements a 3 input NOR function i e F A B C 1 point Complete the corresponding truth table on the right 2 3 points Show the complementary set of transistors that complete the following CMOS gate A B D Y Vdd C 1 point Which Boolean expression is implemented by this circuit Answer Y Comp 411 Fall 2015 1 of 4 Final Exam Sample Questions 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 2 points For the Boolean function described by the truth table on the right write down the corresponding sum of products Boolean expression X Y Z Answer Z 0 1 1 0 Y 1 0 1 0 1 1 0 0 S1 1 0 1 1 S0 4 1 points On the right is a circuit made up of 2 to 1 multiplexers Give the values of S0 and S1 for which the output Y is zero Answer 1 point Give a Boolean equation for Y or for Answer Y your choice in terms of S0 and S1 5 3 points Suppose we want to multiply two large numbers each up to 512 bits wide We are looking at implementing a 512 bit simple combinational multiplier If someone tells us that a 16 bit simple combinational multiplier has a worst case propagation delay of 200 nanoseconds what is the worst case propagation delay of the 512 bit design Answer 6 2 points When checking the equality of two unsigned numbers A B which one or more of the following flags need to be checked Z N C V Answer Comp 411 Fall 2015 2 of 4 Final Exam Sample Questions 7 1 point Suppose you wanted to set certain bits of an operand to 1 while keeping the remaining ones as they are Which of the following logical operations would you use AND OR XOR NOR Answer 8 2 points Can the number 9 5 be exactly represented by an IEEE single precision floating point number Briefly explain your answer 9 2 points Suppose two single precision floating point numbers are multiplied with E field exponent bias values of 50 and 45 respectively What can you say about the value of the E field of the result 10 1 point How is the number zero represented in IEEE single precision floating point 11 3 points Refer to the following picture of a latch not an edge triggered flipflop but a simple positive latch For the input waveforms shown for CLK and IN draw the output waveform for OUT Assume that setup hold times and propagation delay are negligible Comp 411 Fall 2015 3 of 4 Final Exam Sample Questions 12 3 points Refer to the following circuit Suppose the propagation delay of each flipflop is 1 ns i e the delay from the up transition of the clock to the data appearing at the flipflop s output and suppose that the setup time for each flipflop is also 1 ns and the hold time is zero What is the maximum latency allowable for the block of combinational logic if the clock must be run at 100 MHz 13 3 points List the state of all of the control signals that the control logic must generate for the srav instruction PCSEL SEXT ALUFN ASEL WERF WASEL WDSEL Wr BSEL There will be 20 25 questions on the actual exam Comp 411 Fall 2015 4 of 4 Final Exam Sample Questions
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