Summary Caches serve as high speed storage that holds frequently accessed data reducing the time a processor spends waiting for data from slower main memory I learned that the effectiveness of a cache is defined by its design parameters size associativity block size and replacement policy These factors collectively determine the cache s hit rate latency and overall impact on system performance A fundamental concept of caches is temporal and spatial locality the tendency for programs to access the same memory locations repeatedly temporal and for nearby memory locations to be accessed consecutively spatial By leveraging these patterns caches ensure faster data retrieval contributing to smoother execution of programs Additionally the hierarchical structure of modern memory systems often includes multiple levels of caches L1 L2 and sometimes L3 each balancing trade offs between speed size and complexity While L1 is typically the smallest and fastest L3 caches are larger and shared among cores but slower Understanding how these levels interact was crucial in grasping how caches support multi core processors and parallel workloads Confusion Despite understanding the theory behind caches I find it challenging to comprehend the practical trade offs in real world cache design For example increasing cache size can improve hit rates but might also lead to higher latency and power consumption Similarly the nuances of replacement policies such as LRU Least Recently Used versus Random Replacement are still somewhat unclear to me especially in scenarios where workloads are unpredictable or do not exhibit strong locality I also struggle to conceptualize how cache coherence protocols operate in multi core processors to maintain data consistency Protocols like MESI Modified Exclusive Shared Invalid add complexity and understanding their performance implications in modern architectures remains an area I need to explore further