Spring 2011 Prof. Hyesoon Kim• Atom Processors• 32-bit, Hyper-threading, low-power, in-order processors http://en.wikipedia.org/wiki/File:Atom_Z520_vs_1Cent.JPGdesktop• L1 (32KB I-cache, 24K D-cache) • L2 cache (512KB )• Hardware prefetcher• In-order processorBreak_away_with_intel_atom_processors• 16-stage pipeline • 128-bit data path • Hyper-threading (SMT): 2-way supporthttp://www.hardwaresecrets.com/article/Inside-Atom-Architecture/615/2• Idle power management• Aggressive power gating• Speed step• C-state/C-modeVinV outV ddCLV ddVccI leakage0DynamicStatic• f ∞ V P ∞ V3• Set different frequency change power consumption • Save idle power• P-states • Thermal control (dynamic thermal management)• Sleep signal to turn off the supply voltage• Save both dynamic power and leakage powerPower blockerVirtual Vdd(V)Microarchitectural Techniques for Power Gatingof Execution Units, Hu et al.• Longer wake up time, lower leakage power consumption• Provide multiple sleep mode Power Gating with Multiple Sleep Modes• Adds additional logic to a circuit to prune the clock tree• Simplest gating mechanism • Reduce dynamic power consumption• Power up delay (timing problem)• Variations in currentModeNameC0Operating StateCPU fully turned onC1HaltStop CPU clock via software but interface are runningC1EEnhanced HaltStop CPU clock via software, reduce voltage, interface are runningC2EExtend stop Grant~=C1E but via hardwareC3SleepStop all CPU internal clocksC4Deeper SleepReduce CPU voltageC4E/C4Enhanced Deeper SleepReduce CPU voltage and turns off the memory cacheC6Deep Power DownReduce CPU voltage close to 0W0Base line W1 W2 W3W0 W1 B#2 B#3Reduced L2Control number of Ways• Is this OK?• What about Multiple caches? • Flush the cache generate write back requests sleep W0 W1 W2 W3: dirty blockCore 1Core 2$1$2• Atom can put any thread into any C1, C2,or C4 states• C4 or C4E support dynamic cache sizing • PLL (Phase Locked Loop): interface logic• Progress Meeting • Each team 6
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