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UTD CS 5348 - Section 1: Computer System Overview

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Section 1: Computer System Overview Question 1 What are the three regions / utilizations of a program / process’s memory we have discussed in class? Describe briefly how each region is used. Answer 1. Instruction Memory – This is read-only memory that maintains the process’s instructions that are referenced by the PC and executed by the processor. 2. Data (Heap) Memory – This is the memory that is allocated to the process when a process requests (malloc) memory from the operating system. 3. Control Stack – The region of memory that maintains the process’s stack. The stack is used to push function arguments and pop return values from a function call. Question 2 A. Describe the two components of the Generic Instruction Format presented in the book and slides. B. What is the purpose of the PC register? C. What is the purpose of the IR register? D. What is the purpose of the SP register? Answer A. The generic instruction format included both the opcode and address regions. The OPCODE provides bits that describe the instruction / operation the process is to perform. The ADDRESS provides the address of the memory word of the instruction is to operate on. B. The PC is the Program Counter register and contains the address of the instruction being executed. C. The IR is the Instruction Register and contains the currently executing instruction (OP Code). D. The SP is the Stack Pointer register and contains the address of the top of the stack. Question 3 A. Describe the two stages of the processor’s Instruction Execution Cycle. B. Describe how interrupt processing is integrated into the execution cycle. See Figure 1.7.Answer A. Fetch Stage – The instruction referenced by the Program Counter is read from instruction memory and placed into the processor’s instruction register (IR). Execution Stage – The instruction (op code) in the IR is executed by the processor according to the logic hardwired into the processor’s circuitry / microcode. B. Before the next program instruction is executed, the processor hardware checks if the interrupt signal (IRQ) has been raised. If so, processor saves the processor’s (program’s) state and the next instruction fetched and executed will be the first instruction of the interrupt handling code. Question 4 A. What is the definition of ‘asynchronous events’ as described in the slides and book? B. Describe 3 examples of asynchronous events generated by computer system hardware. Answer A. An asynchronous event is an event that occurs independently of the main program flow. It is an event that can occur at any moment i.e. the processor has no means of predicting when these events will occur. Interrupts are the mechanism used in hardware design to ‘notify’ the processor of the occurrence of an asynchronous event that requires the processor’s attention. B. Examples event sources include: - The user pressing a keyboard key or moving the mouse. - The arrival of network message. - A hardware controller that requires attention. (Note to grader: Any three reasonable event sources is acceptable). Question 5 A. Describe the meaning of ‘polling a hardware device’. B. What is the problem with device polling describe in class and book? C. How does the use of interrupts eliminate the need for polling? Answer A. Polling describes a situation where the processor determines if a hardware device requires attention by checking its status aka polling. Polling requires that the processor must repeatedly query the device to determine when the device requires attention i.e. Are you ready? Are you ready? Etc.B. Polling wastes processing resources by repeatedly querying the device (possibly millions of times) to determine when the device requires its attention. These are processing resources that would be better spent executing user programs. C. Devices can generate interrupts at the moment they require processor attention. The processor can instantly respond to these asynchronous events (signals) when they occur i.e. key & button presses, sensors, alarms, and other devices can produce signals that the system must respond to at any time. Question 6 A. In terms of program execution, why do we call this mechanism an “Interrupt”? B. What do we call the instructions executed in response to an interrupt signal? C. Where is the state of the interrupted (currently executing) program stored? Answer A. It is called an interrupt because the occurrence of the event ‘interrupts’ the currently executing program instructions. Because the events are asynchronous, an event can occur at any point in the currently executing program’s execution. B. The instructions that are executed in response to the interrupt are called the ‘Interrupt Handler’. The operating system provides interrupt handlers for each of the devices installed on the system. C. When an interrupt signal is detected by the processor, the state of the currently executing program is saved (pushed) onto the control stack where it later retrieved to restore the execution of the interrupted program when the interrupt handler has completed. Question 7 Describe the “Locality of Reference” principle and provide the two examples discussed in class. How does LOR make cache memory effective? Answer The principle states that a program’s execution will tend to remain in distinct regions of memory addresses over time before moving to new regions. The program will tend to access the same instructions or data (heap) memory many times over a period time. For example: 1) If a program execute the instruction at location i, it is likely to execute instruction i+1. 2) A program may iterate over a list or array of data many times accessing both the data and the loop’s instructions.If the processor hardware can move the referenced blocks of memory from main memory into cache memory when the block is first accessed, instructions and/or data will be found in cache (hit) for all the remaining access while in a region and the overall execution of the program / process will be that much faster. Question 8 What is the average time in us to access a byte in a two level memory if … • Time to access level 1 is 0.1 us. • Time to access level 2 is 1.0 us. • The hit ratio is 96%. Answer 0.96 (.1us) + 0.04 (.1 us + 1us) = 0.14us Question 9 A. Describe the reason for a cache replacement policy in processor design. B. What should a cache

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