EE 110 Homework 9 Spring 2017 CQUPT 1. Design a 3-bit sequencer that implements the following state sequence. Use three D flip-flops whose clock inputs are connected to CLK. The state bits are Q2, Q1, and Q0. Show the full state table (10 points). Use K-maps to minimize your equations (15 points). Show the logic diagram for your complete design (15 points). 2. Design a 3-bit sequencer that implements the following state sequence. Use three JK flip-flops whose clock inputs are connected to CLK. The state bits are Q2, Q1, and Q0. Show the full state table (20 points) including all J and K input values. Use K-maps to minimize your equations (15 points). Show the logic diagram for your complete design (15 points). Note: Although there is no way for the system to reach states 5 and 7 under normal operation, it could actually arrive at either of those states upon power up. If that happens, the system will reach the main sequence in only one clock
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