EE 110 Spring 2017 CQUPT Homework 8 1. (10 points) Given the SR flip-flop below, complete the timing diagram by determining the output Q. Note that the flip-flop is triggered on the rising edge of the clock signal. The condition S=R=1 is produced twice by the inputs. Will this lead to unstable operation? Explain. 2. (10 points) Given the JK flip-flop below, complete the timing diagram by determining the waveform of the output Q. This flip-flop is triggered on the falling edge of the clock signal. 3. (20 points) Derive the state diagram and characteristic equation of the latch circuit below.4. (20 points) Given the following circuit, complete the timing diagram below by drawing the waveforms of signals Q1 and Q2. Notice that the D flip-flop is negative edge triggered and the JK flip-flop is positive edge triggered. The R input of each flip-flop is an asynchronous reset line. 5. (10 points) The waveforms below are applied to a JK flip-flop having a positive edge triggered clock input. Complete the timing diagram by drawing the waveforms of flip-flop outputs € Q and €
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