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UTD CS 6363 - Assignement

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11/9/2017 Assignement_6file:///var/folders/jb/gp_rc7054lbfqxzmc73xdt0m0000gn/T/mume117109-673-11ci8ar.oc3ntmaemi.html 1/34.1 Consider the following instruction: Instruction: AND Rd,Rs,Rt Interpretation: Reg[Rd] = Reg[Rs] AND Reg[Rt] 4.1.1 [5]<§4.1>What are the values of control signals generated by the control in Figure 4.2 for theabove instruction? 4.1.2 [5] <§4.1> Which resources (blocks) perform a useful function for this instruction? 4.1.3 [10] <§4.1> Which resources (blocks) produce outputs, but their outputs are not used for thisinstruction? Which resources produce no outputs for this instruction?A:4.1.1RegWrite MemRead ALUMux MemWrite ALUop RegMux Branch1 0 0 0 AND 0(ALU) 04.1.2 The resources that perform a useful function for this instruction are all blocks except Data Memory andbranch Add unit.4.1.3 For this instruction, the outputs that are not used is branch add. The on outputs for this instruction isData Memory.4.2 The basic single-cycle MIPS implementation in Figure4.2 can only implement some instructions.New instructions can be added to an existing Instruction Set Architecture (ISA), but the decisionwhether or not to do that depends, among other things, on the cost and complexity the proposedaddition introduces into the processor data path and control. The first three problems in this exerciserefer to the new instruction:Instruction: LWI Rt,Rd(Rs) Interpretation: Reg[Rt] = Mem[Reg[Rd]+Reg[Rs]] 4.2.1 [10] <§4.1> Which existing blocks (if any) can be used for this instruction? 4.2.2 [10] <§4.1> Which new functional blocks (if any) do we need for this instruction? 4.2.3 [10] <§4.1> What new signals do we need (if any) from the control unit to support this instruction?A:11/9/2017 Assignement_6file:///var/folders/jb/gp_rc7054lbfqxzmc73xdt0m0000gn/T/mume117109-673-11ci8ar.oc3ntmaemi.html 2/34.2.1 The instruction which used the blocks are including instruction memory, Read Registers, the ALU anddata memory and write Registers.4.2.2 The new functional blocks we need no new functional blocks for this instruction.4.2.3 Nothing new blocks we need from the control unit to support this instruction.4.3 When processor designers consider a possible improvement to the processor datapath, thedecision usually depends on the cost/performance trade-o . In the following three problems, assumethat we are starting with a datapath from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, andControl blocks have latencies of 400 ps, 100 ps, 30 ps, 120 ps, 200 ps, 350 ps, and 100 ps,respectively, and costs of 1000, 30, 10, 100, 200, 2000, and 500, respectively. Consider the addition of a multiplier to the ALU. is addition will add 300 ps to the latency of the ALUand will add a cost of 600 to the ALU. e result will be 5% fewer instructions executed since we will nolonger need to emulate the MUL instruction. 4.3.1 [10]<§4.1>What is the clock cycle time with and without this improvement? 4.3.2 [10] <§4.1>What is the speedup achieved by adding this improvement? 4.3.3 [10] <§4.1> Compare the cost/performance ratio with and without this improvement.A:4.3.1 The clock time without improvement is: 400ps+200ps+30ps+120ps+350ps+30ps=1130ps After improvement is 1130ps+300ps=1430ps4.3.2 we have a speedup of 4.3.3 The cost is the total cost of all the blocks. Since there are I-Mem,Regs,Control,ALU,D-Mem,2Add units and 3 Mux units. So the total cost is1000+200+500+100+2000+230+310 = 3890 The cost after improvement is :3890+600 = 4490 The ratio without improvement is : (3890/3890)/1 =1 The ratio with improvement is : (4490/3890)/0.83=1.39( × ) = 0.8310.951130143011/9/2017 Assignement_6file:///var/folders/jb/gp_rc7054lbfqxzmc73xdt0m0000gn/T/mume117109-673-11ci8ar.oc3ntmaemi.html

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