EEL 4768C: Computer ArchitectureReview of Single‐Cycle Datapathand Multi‐Cycle Datapath2Question 1. Give the values of all the contr ol signals when the “load word” (lw) instruction is in the CPU. Give the value as “1”, “0” or “X” (for don’t care).RegDst: 0Branch: 0MemRead: 1MemtoReg: 1ALUOp: 00 (will do add)MemWrite: 0ALUSrc: 1RegWrite: 13Question 2. We need to add the “exclusive or” (xor) instruction in the single‐cycle datapath. What changes do we need to make?“xor” is an R‐type instruction. The datapath that we have can ex ecute R‐type instructions. A typical R‐type instruction needs to (1) fetch 2 registers, (2) use the ALU and (3) write the result to a register.The “xor” has the opcode “000000” similar to all R‐types (format in figure below). When the control unit sees this opcode, it will set ALUOp=10. It means, the ALU control unit will look at the FUNC field, which are the rightmost 6 bits of the instruction. For “xor”, FUNC=38.26hex=384opcode ALUOp Operation funct ALU function ALU control000000 (0) 10 add 100000 add 0010subtract 100010 subtract 0110AND 100100 AND 0000OR 100101 OR 0001set-on-less-than 101010 set-on-less-than 0111The table below, shows the FUNC fields for the instructions that we already have. We need to give “xor” a FUNC value that’s not used. We select any value that’s not used. The MIPS format for “xor” uses the value 38=100110, so we use this value.We need to redo the ALU control unit to recognize the FUNC field of the XOR operation. The ALU control unit generates a 4‐bit ALU control field that tells the ALU what operation should be done.ALU Control5ALU control Function0000 AND0001 OR0010 add0110 subtract0111 set‐on‐less‐thanFinally, we need to update the ALU so it can do the “xor” operation. For every operation, the ALU tak es a 4‐bit ALU control field. We need to give the “xor” operation such a field. This field will be generated by the ALU control unit to request an “xor”.6We don’t need to make any change to the control unit. All the control signals will be set the same as in any other R‐type instruction.RegDst: 1Branch: 0MemRead: 0MemtoReg: 0ALUOp: 10 (use FUNC)MemWrite: 0ALUSrc: 0RegWrite: 17Question 3. Modify the single‐cycle datapath so it implements the “jump‐and‐link” (jal) instruction. The “jal” instruction saves the PC+4 value in the return address ($ra) register.In previous examples, we showed the usefulness of “jal”. Before branching to a procedure, we use “jal”. The return address is saved in $ra. At the end of the procedure, we use “jr $ra” (Jump‐to‐register) so that we can get back to the main code.Example of using “jal”96: addi $a0, $s1, $s2 # This is an argument to the procedure100: addi $a1, $s3, $s4 # This is an argument to the procedure104: jal FindMax # Jump to FindMax. Saves 108 in $ra108: sw $v0, 0($t7) # Print the returned answer…FindMax:400: slt $t0, $a0, $a1 # (if a0<a1, t0=1), (if a0>=a1, t0=0)404: beq $t0, $zero, Returna0408: add $v0, $zero, $a1412: j End416: Returna0: add $v0, $zero, $a0End:420: jr $ra # Go to address 108, at the “sw” instruction8What does “jal” do?The MIPS instruction format of “jal” is shown below.It acts as a jump. The jump address is computed similar to a “j” instruction.On top of that, it saves PC+4 in the return address register ($ra).…104: jal FindMax # Jump to FindMax. Saves 108 in $ra108: sw $v0, 0($t7) # Print the returned answer…9We need the PC+4 value to be saved inside a register. By looking at the datapath below, we see that there’s no way for the PC+4 (output of adder) to be sent to a register. We need to modify the datapath.PC+4Data written into a register10We add a new line that tak es the PC+4 and sends it to the “Write Data” input of the register file. We need to add a multiplexer. We also need to make sure the “Write Register” field is set to the address of $ra. Register $ra is register number 10.01Original “Write Data”New line from PC+4Selector: jal control signal“Write Data” input of register01Original “Write Register” from output of mux controlled by RegDst01010($ra is reg 10)Selector: jal control signal“Write Register”input of registerWe add two multiplexers to make these connections.1101Original “Write Data”New line from PC+4Selector: jal control signal“Write Data” input of register01Original “Write Register” from output of mux controlled by RegDst01010($ra is reg 10)Selector: jal control signal“Write Register”input of registerThe main control unit generates an additional signal called “jal”. This signal is equal to 1 only for the “jal” instruction.The MIPS format of the “jal” instruction is shown below. It uses opcode=3, so the control unit recognizes it through this opcode.12The main control unit should produce these control signal values when the “jal” instruction is in the data path.jal: 1RegDst: XBranch: 0MemRead: 0MemtoReg: XALUOp: XXMemWrite: 0ALUSrc: XRegWrite: 113Question 4. Modify the single‐cycle datapath so it implements the “jump‐to‐register” (jr) instruction. The “jr” jumps to the 32‐bit address that’s stored inside a register. Typically, it’s used as “jr $ra” to jump to the return address after finishing a procedure.14This is the format of the “jr” instruction in MIPS. It has the opcode=0. Accordingly, the main control unit will treat “jr” as an R‐type. Therefore, we don’t have to spend one unique opcode for “jr”.Let’s see how the R‐type control allows this instruction to be implemented. Below are control values for the R‐type instructions.* For “jr”, we don’t care about RegDst since we’re not writing to a register.* Branch should be 0.* MemRead should be 0.* We don’t care about MemtoReg since we’re not writing to a register.* ALUOp is 10. This tells the ALU control that it’s either an R‐type or “jr” instruction.* MemWrite should be 0.* We don’t care about ALUSrc since we’re not using the ALU* Even though RegWrite is 1, nothing will be written to the registersince the field “rd” is equal to 0. The register $zero is not modifiedeven if an instruction attempts to modify it.Accordingly, everything is ok to treat “jr” as R‐type in the controlunit.RegDst: 1Branch: 0MemRead: 0MemtoReg: 0ALUOp: 10 (use FUNC)MemWrite: 0ALUSrc: 0RegWrite: 115According to “jr” instruction format, the