UA ECE 486 - Quiz 3 (2 pages)

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Quiz 3



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Quiz 3

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Pages:
2
School:
University of Alabama
Course:
Ece 486 - Embedded Systems

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Quiz 3 ECE 486 586 Spring 2005 Name Student Number 1 Consider the characteristics of a memory system given below Cache size 512 bytes Main memory size 4096 bytes Cache line block size 64 bytes Replacement policy least recently used Write policy write back Assume the cache is initially empty meaning that no cache blocks are considered valid at the start of the program Assume a program to be executed on this system generates the following sequence of main memory byte addresses 0 512 130 800 60 1024 NOTE Show all your work on all parts of the problem What is the best possible hit rate for this sequence of addresses 5 points We have 6 different main memory addresses but only two of them are in the same main memory block 0 and 60 Therefore the only possible hit is for memory address 60 to reside in the cache when referenced since its main memory block was referenced previously So possible hit rate 1 6 16 67 For a 4 way set associative cache configuration what is the hit rate 5 points mm address 0 512 130 800 60 1024 tag binary 00000 00100 00001 00110 00000 01000 index binary 0 0 0 0 0 0 offset binary 000000 000000 000010 100000 111100 000000 mm blk 64 0 8 2 12 0 16 hit rate 1 6 16 67 Calculate the total size of the cache 5 points cm set 2 0 0 0 0 0 0 cm blk 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 hit miss miss miss miss miss hit miss Total cache size 8 blks 64 bytes 8 blks 5 bits for tag 8 blks 1 bit valid bit 8 blks 1 bit dirty bit 512 bytes 40 bits 8 bits 8 bits 519 bytes Finally draw the cache and indicate which main memory blocks reside in each cache block AFTER the sequence of memory references is completed 15 points D x x x x 0 0 0 0 V 1 1 1 1 0 0 0 0 Tag 00000 01000 00001 00110 xxxxx xxxxx xxxxx xxxxx Data mm blk 0 mm blk 16 mm blk 2 mm blk 12 cache blk 0 1 2 3 4 5 6 7 cache set 0 0 0 0 1 1 1 1 NOTE The cache block number and the cache set number are NOT part of the cache They are only used to show the organization of the cache



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