CORNELL CS 3410 - 3410_2016sp_prelim2_soln (10 pages)

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3410_2016sp_prelim2_soln



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3410_2016sp_prelim2_soln

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Pages:
10
School:
Cornell University
Course:
Cs 3410 - Computer System Organization and Programming
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Prelim 2 Computer Science 3410 Cornell University Spring 2016 Prof Bracy 5 May 2016 Solutions 1 Data and Control Hazards 16 pts a 8 pts Forwarding In the pipeline below the register file is read in the 1st half of the cycle and written in the 2nd half of the cycle Bypasses 1 5 are shaded In the D X latch the 1st operand to an ALU instruction is stored in the A slot of the latch The 2nd operand is stored in the B slot of the latch 5 4 3 A inst mem Register File rA rB rD D D 2 B a 1 inst inst D lw r5 0 r2 d B S X F M Data Mem inst X sub r4 r2 r3 inst M sw r3 0 r2 W addi r2 r1 1 For each input specified below state where the instruction gets its data 15 refer to the bypasses shown in the above figure RF stands for register file ERROR means that the instruction cannot possibly get its data in order to execute correctly given the processor above and the timing specified in the diagram Circle One r2 of the sw 1 2 3 4 5 RF ERROR r2 of the sub 1 2 3 4 5 RF ERROR r3 of the sub 1 2 3 4 5 RF ERROR r2 of the lw 1 2 3 Answer 4 3 RF ERROR 4 5 RF ERROR b 8 pts Control Dependences Suppose we had asked you to implement a 2 instruction control delay slot for Project 2 In other words the next two instructions immediately following a control instruction will always be executed Which of the following statements about this concept are true Check all that apply 1 2 delay slots would be harder to implement in Logisim than 1 It will be harder for a compiler to fill the 2nd delay slot than to fill the 1st Processors with 1 delay slot benefit more from branch prediction than one with 2 delay slots A processor with 2 delay slots might support a faster clock than one with only 1 Answer Items 2 4 should be checked Item 1 is not not true 2 ISAs 8 pts For each multiple choice question there is only one correct answer a 2 pts A B C D E It naturally supports a faster clock Instructions are easier to decode The static footprint of the code will be smaller The code is easier for a compiler to optimize You have a lot of registers to use Correct Answer C b 2 pts A B C D E What is one advantage of a CISC ISA What processor feature does a compiler not need to know about There is a control delay slot The number of inputs each instruction can have The processor performs statically scheduled multiple issue execution The processor performs dynamically scheduled multiple issue execution Whether the processor supports predication Correct Answer D c 2 pts What is not a good reason to limit the number of instructions offered by a particular ISA A Offering more instructions leads to executables with more static instructions B More complicated instructions are difficult to pipeline C More instructions may lead to needing more bits in the opcode field which could make static instructions larger D It is very difficult to ever stop supporting a particular instruction once it has been added to the ISA E More instructions will complicate the decode logic of the processor Correct Answer A 2 d 2 pts Which of the following statements about ISAs is true A Because clock frequencies are no longer increasing a return to CISC ISAs makes sense B Which cache coherence protocol is implemented needs to needs to be specified in the ISA C Atomic operations need to be specified in the ISA D ISA design has stagnated no new ISAs of any commercial significance have appeared in the past 10 years E A system call is OS specific and not an ISA level feature Correct Answer C 3 Calling Conventions 16 pts The following assembly is the body of a function compiled for a MIPS processor with a control delay slot Body Loop Exit addiu s3 a0 0 addiu s5 a1 0 addiu s6 a2 0 sll t1 s3 2 add t1 t1 s6 lw t0 0 t1 bne t0 s5 Exit nop addi s3 s3 1 j Loop nop addiu a0 s3 0 jal record nop addiu v0 s3 0 Write the prologue and epilogue for this body Use the class calling conventions PROLOGUE ADDIU sp sp 36 SW ra 32 sp SW fp 28 sp SW s3 24 sp SW s5 20 sp SW s6 16 sp ADDIU fp sp 32 EPILOGUE LW s6 16 sp LW s5 20 sp LW s3 24 sp LW fp 28 sp LW ra 32 sp ADDIU sp sp 36 JR ra NOP 3 4 Linkers and Loaders 10 pts Below is a modified version of heaptest c from Project 4 include stdio h include heaplib h define HEAP SIZE 16 static int ARR SIZE 4 int main char heap HEAP SIZE hl init heap HEAP SIZE sizeof char char ptr char hl alloc heap ARR SIZE sizeof char ptr 0 h ptr 1 i ptr 2 0 printf s n ptr return 0 Where does the assembler place each of the following symbols from the above program in the object file that it creates Choose one a Text Segment b Data Segment c Exported reference in the symbol table d Imported reference in the symbol table e None of the above Circle One 1 HEAP SIZE E 2 ARR SIZE B 3 heap E 4 hl init D 5 h B 4 5 Caches 24 pts parts a d a 9 pts For each workload choose the best block size for your cache among the choices given Assume that integers and pointers are all 4 bytes each Use the intuitions you have developed in this class to decide what best means for a cache Choose one a 1 byte b 4 bytes c 8 bytes d 16 bytes e 32 bytes BEST BLOCK SIZE Circle One int scores NUM STUDENTS 0 A B C D E int sum 0 for i 0 i NUM STUDENTS i sum scores i typedef struct item t int value item t next char name item t A B C D E int sum 0 item t curr list head while curr NULL sum curr value curr curr next H 16 W 16 int A H W Assume a 256 byte cache for x 0 x W x for y 0 y H y sum A y x A B C D Answers E C B b 9 pts Memory Access Time Processor A is a 1 GHz processor 1 cycle 1 ns There is an L1 cache with a 1 cycle access time and a 50 hit rate There is an L2 cache with a 10 cycle access time and a 90 hit rate It takes 100 ns to access memory 3 points What is the average memory access time of Processor A in …


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