CORNELL CS 3410 - 3410_2016sp_prelim2_soln (10 pages)

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3410_2016sp_prelim2_soln



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3410_2016sp_prelim2_soln

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Pages:
10
School:
Cornell University
Course:
Cs 3410 - Computer System Organization and Programming

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Prelim 2 Computer Science 3410 Cornell University Spring 2016 Prof Bracy 5 May 2016 Solutions 1 Data and Control Hazards 16 pts a 8 pts Forwarding In the pipeline below the register file is read in the 1st half of the cycle and written in the 2nd half of the cycle Bypasses 1 5 are shaded In the D X latch the 1st operand to an ALU instruction is stored in the A slot of the latch The 2nd operand is stored in the B slot of the latch 5 4 3 A inst mem Register File rA rB rD D D 2 B a 1 inst inst D lw r5 0 r2 d B S X F M Data Mem inst X sub r4 r2 r3 inst M sw r3 0 r2 W addi r2 r1 1 For each input specified below state where the instruction gets its data 15 refer to the bypasses shown in the above figure RF stands for register file ERROR means that the instruction cannot possibly get its data in order to execute correctly given the processor above and the timing specified in the diagram Circle One r2 of the sw 1 2 3 4 5 RF ERROR r2 of the sub 1 2 3 4 5 RF ERROR r3 of the sub 1 2 3 4 5 RF ERROR r2 of the lw 1 2 3 Answer 4 3 RF ERROR 4 5 RF ERROR b 8 pts Control Dependences Suppose we had asked you to implement a 2 instruction control delay slot for Project 2 In other words the next two instructions immediately following a control instruction will always be executed Which of the following statements about this concept are true Check all that apply 1 2 delay slots would be harder to implement in Logisim than 1 It will be harder for a compiler to fill the 2nd delay slot than to fill the 1st Processors with 1 delay slot benefit more from branch prediction than one with 2 delay slots A processor with 2 delay slots might support a faster clock than one with only 1 Answer Items 2 4 should be checked Item 1 is not not true 2 ISAs 8 pts For each multiple choice question there is only one correct answer a 2 pts A B C D E It naturally supports a faster clock Instructions are easier to decode The static footprint of the code will be smaller The code is easier for a compiler to optimize You have a lot of registers to use Correct Answer C b 2 pts A B C D E What is one advantage of a CISC ISA What processor feature does a compiler not need to know about There is a control delay slot The number of inputs each instruction can have The processor performs statically scheduled multiple issue execution The processor performs dynamically scheduled multiple issue execution Whether the processor supports predication Correct Answer D c 2 pts



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