Emerging Opportunities for Future Analog Design Mike ChenEEAB meeting 3/31/2011About myself• PhD, UC Berkeley 06’. Atheros Comm. 10’. USC 11’.• Wireless / Wireline Communications– UWB, WiFi, GPS, Bluetooth, USB, PCIe.• Integrated Circuit Design– Analog: CMOS mixed-signal, RF circuits for UWB, WiFi (820.11a/b/g/n), GPS, USB.– Digital VLSI: UWB baseband processor– SOC: fully integrated radio chip• Signal Processing– Optimize radio architecture– Fix analog circuit impairmentsWhere is IC world standing today?• CMOS dominates modern commercial ICs.• High-level of integrations.• Complex system functionality. • Fortunately, more transistors per area, due to scaling.  SOC• Two observations:- Favors digital.- Favors speed.2003 ITRS - Silicon CMOS1010010001995 2000 2005 2010 2015 2020Production YearTechnology Node [nm]100100010000NMOS Peak fT [GHz]MPU printed gate lengthNMOS peak transit freq.4Analog designers’ dilemmaW,L 1/SSupply 1/SArea 1/S2Power 1/S2Speed SMatching (1/WL)Linearity (Vdsat)Noise (4KTggm)Gain (gm*ro)Ft (gm/C)XDigital ScalingAnalog ScalingXXXO5Relax system specification?• But… how is it possible?• Most systems are demanding more computations, higher energy efficiency, small form factor, and cheaper price!• Analog circuit design implications wider bandwidth, higher dynamic range, higher power efficiency, smaller area, use scaled technology!6System asks for more…• Multiple standards  Combo radios, SDR• Multiple antenna  802.11n, WiMax• Intelligence  Cognitive radio, Coexistence• Wideband  60 GHz, UWBGSM/EDGEGPSUMTS/HSDPAWiFiTV BandUWB60 GHzBTWireless SpectrumMore dynamic range, bandwidth, functionalities, …Emerging constraints for analog design• Increasing variability  mismatch, leakage.• Higher energy efficiency  data converter, PA.• Smaller area  passive components R, L, C.• More programmability.  reconfigurable analog.• How to resolve the constraints:1. Digitalized2. Timed3. RandomizedDigitalized Analog: PLLDigitalAnalogPFD CP/NFref-Leakage-Area consuming-Headroom-Matching-NoiseAnalogDigital/NFrefDACDigitalFilterQuan.PFD-No leakage-Noiseless-Small areaDigitalized Analog: PLL Example• Chip area is reduced by 300% compared to an analog PLL.• No more bulky and leaky analog R, C components. • More programmability/accessibility.• Technology scalability.• Leverage digital design environment. • Fulfill a lazy analog designer’s dream.M. Chen, et al, ISSCC 2010Digitalized Analog: PLL Next• Remaining challenges in this area.- How to diminish the ADC cost? - How to reduce the spurious tones and spectral images due to ADC and DAC?- How to leverage the usage of a digital PLL, now that the main computation is done in digital domain?• Fantastic, if we can…- Synthesize a PLL, as if another digital IP block.Digitalized Analog: PA (I)• Efficiency is the key, and linearity is the bottleneck for linear PAs.  Digitally pre-distort the signal.Ref: http://www.mwrf.com/Article/ArticleID/16344/16344.htmlhttp://www.xilinx.com/publications/prod_mktg/pn2061.pdfDigitalized Analog: PA (II)• Digital polar (EER) architecture. Linearly combine the amplitude path utilizing constant-envelope unit PAs.• 3~4X efficiency improvement for 12dB power backoff.Ref: A. Kavousian, et al, JSSC 2008.Digitalized Analog: PA Next• ADC and DAC plays important roles in various digital PA architecture. How to diminish their cost and improve precision?• How to leverage high-speed switching and reduce switching loss?• DSP opportunities to condition the signal, such as linearization, filtering, mixing, etc.Digitalized Analog: ADC• Paradigm shift in ADC is relying more digital than analog. • Numerous digital calibration techniques have been demonstrated to use low-precision analog circuits, and applied to almost every ADC topology.VrefDecoderVinCLKVinDecoderCLKDACS/H ADC DAC+Stage1StageNStage iDigitalized Analog: ADC Next• Recent focus on time-interleaving for high-speed operation. • Effective calibration across the different branches remain a big challenge. A recent example (56GS/s) parallelizes 320 unit ADCs!Ref: Schreier, "ADCs and DACs: Marching Towards the Antenna," GIRAFE workshop, ISSCC 2003Timed Analog: TDC• Explore time axis (beyond voltage, current).• Time-to-digital converters (TDC) or digital-to-time converters (DTC) are emerging in various mixed-signal circuits.• Logic delay scales down and offers better precision.TDCDTCTimed Analog:Digitalized PLLADCDACRandomized Analog: ADC• Asynchronous SAR ADC .ENOBs2FTotal_PWM. Chen, et al, ISSCC 2006Family of Async. Enabled ADCRandomized Analog: Sampling• Asynchronous sampling (continuous time processing)- no aliasing (ADC and DAC)- scale with input activity- interface with async. digital VLSI (fine pipelining, adaptive width, tolerate sub-threshold operation)Ref: Tsividis, TCAS-I, 2010.Conclusion• More digital is marching into daily analog design driven by technology and application. • Timing aspect of the analog circuit remains to be explored. • Randomness can be helpful.• Potentially leverage analog mixed-signal computation beyond