Berkeley ELENG 225C - The Cost of Flexibility in Systems on a Chip Design for Signal Processing Applications

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The Cost of Flexibility in Systems on a Chip Design for Signal Processing ApplicationsI. IntroductionII. Architectural Design Space and Design MetricsA. Architecture SpaceB. Design MetricsC. Relationship Between Architecture and Design Metrics1). Digital Signal Processor2). DSP Extension3). Direct-Mapped Dedicated Hardware4). Architecture Comparison and AnalysisIV. Intermediate ArchitecturesExample: FFTVI. ConclusionReferenceThe Cost of Flexibility in Systems on a Chip Design forSignal Processing ApplicationsNing ZhangAtheros Communications, Inc. and Robert W. BrodersenBerkeley Wireless Research CenterUniversity of California, BerkeleyAbstractProviding flexibility into a system on a chip design is sometimes required and generallyalways desirable. However the cost of providing this flexibility in terms of energyconsumption and silicon area is not well understood. This cost can range over manyorders of magnitude depending on the architecture and implementation strategy. Toquantify this cost, efficiency metrics are introduced for energy (MOPS/mW) and area(MOPS/mm2) and are used to compare a variety of designs and architectures for signalprocessing applications. It is found that the critical architectural parameters are theamount of flexibility, the granularity of the architecture in providing this flexibility andthe amount of parallelism. A range of architectural solutions which tradeoff theseparameters are presented and applied to example applications.I. IntroductionThe tradeoff of various types of architectures to implement digital signal processing(DSP) algorithms has been a subject of investigation since the initial development of thetheory [1]. Recently, however the application of these algorithms to systems that requirelow cost and the lowest possible energy consumption has placed a new emphasis ondefining the most appropriate solutions. For example, advanced communicationalgorithms which exploit frequency and spatial diversities to combat wireless channelimpairments and cancel multi-user interference for higher spectral efficiency (data rate /bandwidth) have extremely high computational complexity (10’s-100’s of billions ofoperations/second), and thus require the highest possible level of optimization. 1In order to compare various architectures for these complex applications it is necessary todefine design metrics which capture the most critical characteristics relating to energyand area efficiency as a function of the flexibility of the implementation. Flexibility inimplementing various applications after the hardware has been fabricated is a desirablefeature, and as will be shown it is the most critical criteria in determining the energy andarea efficiency of the design. However, it is found that there is a range of multiple ordersof magnitude differences in these efficiencies depending on the architecture used toprovide various levels of flexibility. Therefore, it is important to understand the cost offlexibility and choose an architecture which provides the required amount at the highestpossible efficiency. Consequently, the flexibility consideration becomes a new dimension in thealgorithm/architecture co-design space. Often the approach to flexibility has been toprovide an unlimited amount through software programmability on a Von Neumannarchitecture. This approach was based on hardware technology assumptions whichassumed hardware was expensive and the power consumption was not critical so thattime multiplexing was employed to provide maximum sharing of the hardware resources.The situation now for highly integrated “system-on-a chip” implementations isfundamentally different: hardware is cheap with potentially 1000’s of multipliers andALU’s on a chip and the energy consumption is a critical design constraint in manyportable applications. Even in the case of applications that have an unlimited energysource, we are now beginning to move into an era of power constrained performance forthe highest performance processors since heat removal requires the processor to operateat lower clock rates than dictated by the logic delays. The importance of architecture design is further underscored by the ever and fasterincreasing algorithm complexity, and purely relying on technology scaling many DSParchitectures will fall short of computational capability for more advanced algorithmsdemanded by future systems. An efficient and flexible implementation of high-performance digital signal processing algorithms therefore relies on architectureoptimization. Unfortunately, the lack of a systematic design approach and consistentmetrics currently prevents the exploration of various realizations over a broad range of2architectural options. The focus of this paper is to investigate the issues of flexibility andarchitecture design together with system and algorithm design and technology to get abetter understanding of the key trade-offs and the costs of important architectureparameters and thus more insight in digital signal processing architecture optimization forhigh-performance and energy-sensitive portable applications.Section II introduces the design metrics used for architecture evaluation and comparisonwith an analysis of the relationship between key architecture parameters and designmetrics. Section III uses an example to compare two extreme architectures: softwareprogrammable and dedicated hardware implementation, which result in orders ofmagnitude difference in design metrics. The architectural factors that contribute to thedifference are also identified and quantified. Section IV focus on intermediatearchitectures and introduces an architecture approach to provide function-specificflexibility with high efficiency. This approach is demonstrated through a design exampleand the result is compared to other architectures.II. Architectural Design Space and Design MetricsA. Architecture Space The architectures being considered range from completely flexible software basedprocessors including both general purpose as well as those optimized for digital signalprocessing (DSP’s), to


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Berkeley ELENG 225C - The Cost of Flexibility in Systems on a Chip Design for Signal Processing Applications

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