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DMA The Hidden Key to DSP Systems



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DMA The Hidden Key to DSP Systems Steve Krueger DSP Architecture Group Dallas What Do DSP Systems Do Process filter scale transform encode decode correlate etc these operations are processor and data intensive Signals generally continuous or nearly continuous streams of sampled real world data usually real time Impediments to Processing Can t process until data is received often a whole block of data Most algorithms have many memory accesses Memory access latency increases with memory size and distance from processor Some operations too specialized for general purpose DSP Model System CoProc Digital Signal Processor Local Mem int Periph Large On Chip Memory off chip data source sink off chip memory DMA Proc a few cycles 10 cycles 50 100 cycles Memory Latency C6400 System Correlation CoProc C6400 DSP 16 kB Mem int McBSP 1024 kB On Chip Memory off chip data source sink off chip memory EDMA a few cycles 10 cycles 50 100 cycles Memory Latency DMA Solves Two Problems I O interrupt loading slows processor work on tasks Data in close memory avoids latency for higher performance Problem of Interrupt Loading Each peripheral usually interrupts to indicate data ready Processor takes interrupt by entering an interrupt handler transferring the data then resuming the interrupted processing This interrupt sequence takes at least 20 cycles on most modern architectures many more on some Interrupts of High Speed Peripheral A high speed peripheral can generate a lot of interrupts say you have a 1 Msps ADC that produces an 8 bit conversion every microsecond If you interrupt for every conversion have 1 million interrupts per second If the interrupt takes 30 cycles this is using 5 of a C6416 at 600 MHz What if your system needs 8 of these Solutions to Interrupt Problem Can buffer at the peripheral and interrupt less frequently Might interrupt once per 32 conversions increases complexity and cost of peripheral adds latency to peripheral data more complex error handling Can make peripheral



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