Laboratory 7 Daniel Choi 904169062 Lab 2a MOSFET logic inverters a We will build the logic inverter below This is an n channel MOSFET and is called an NMOS inverter We plug a DVM at the output and we vary the input voltage The point of doing this is so that we can see the approximate value where we see the switch in logic from true to false or 0 to 1 V Input Voltage V Input vs Output Voltage 6 5 4 3 2 1 0 0 0 5 1 1 5 2 2 5 Output Voltage V V out 0 00V 0 3V 0 6V 1 0V 1 2V 1 6V 1 7V 1 8V 1 9V 2 0V 2 1V 4 97V 4 96V 4 96V 4 936V 4 69V 0 069V 0 022V 0 005V 0 004V 0 001V 0 001V 2 2V 0 001V The plot shows that there is a very specific value for when our NMOS turns on and off which corresponds to the logic of 0 and 1 For our circuit we cannot directly drain to the 5V because it will short the MOSFET and also the MOSFET will not be able to recognize which voltage to use to identify the voltage drop it is meaningless b We now build a PMOS inverter without disassembling our NMOS inverter on another portion of our breadboard using a p channel MOSFET We find that when the input voltage is at 0V the output is 0V which is off When the input is at 1 6V the output is 5V which is on c We now want to find the output impedance of the NMOS inverter Using the thevenin equivalence we find that there is a voltage drop of when using a 10k resistor Thus we can say that the output impedance is 10k The impedances are the same for 1 true and 0 false d We now plug in our function generator into our NMOS inverter We generate a square wave oscillating between 0 and 5V by setting an offset Using a low frequency of about 1kHz we see that the circuit is in fact inverting We now we take a look at our scope to see how long it takes for our circuit to react from 0 1 and 1 0 We see that 0 1 happens in t 7 3 s and 1 0 happens in t 10 13ns The highest baud or bitrate at which our inverter circuit still works was about 85kHz e We now measure the risetimes and falltimes of our NMOS and PMOS inverters The differences in risetimes and falltimes arise for each circuit because there are differences in the mobility of the electrons and holes of our transistor f We will now create a CMOS complementary metal oxide semiconductor using an NMOS and a PMOS We measure the risetime and the falltime for this circuit We see that the risetime is 169ns and the falltime is 271ns We see that it is the combination of the falltime of the NMOS and the risetime of the PMOS The CMOS is the best of both worlds where it significantly reduces the rise and fall times of the circuit We crank up the frequency of our function generator and we see that the highest frequency at which this circuit still works using an input square wave is about 800kHz g Now taking an off the shelf CMOS inverter 74HCT04 we plug it into our breadboard in the following manner We see that each pin has to be either plugged into a 0V or a 5V We plug in our function generator into our input and our scope to the output We run the CMOS with a square wave of 1kHz and amplitude of 5V with an offset of 5V We then lower the input voltage the amplitude and we check to see the range that corresponds to 0 and 1 logic levels We see that our circuit breaks down loses its inverting properties at around 3 1V We see that it still works fin at 3 2V 13 5 Homemade NAND h We build the following circuit We have built our own NAND gate using CMOS logic NMOS and PMOS We measure the following truth table 1 being on 5V and 0 being off 0V Pic 1 A 1 B 0 Q 1 2 0 1 1 3 0 0 1 4 1 1 0 We see that this works like a NAND gate because a path across the output and ground can only be made when both of the NMOS transistors are conducting This only occurs when A and B have a logic of 1 Thus the PMOS are not conducting and all paths are broken such that A B 1 output 0 i We now wire up a NAND chip 74HCT00 and we make the logic table below 1 being on 5V and 0 being off 0V Pic 5 6 7 8 A 1 0 0 1 B 0 1 0 1 Q 1 1 1 0