1 EE555: "Broadband Networks Architecture" Professor A. Zahid, Fall Semester 2007 HW#3: Due Friday, October 5 1. Consider the 3-stage space switch with N = 16, n = 4 and k = 2 a) What is the maximum number of connections that can be supported at any given time? b) For a given set of input-output pairs, Is there more than one way to arrange the connections over the this switch c) Now assume that N = 32. Compare the number of crosspoints required by a non-blocking switch with n = 16, n = 8, n = 4, and n = 2 cases 2. Consider the 3-stage space switch. An input line is busy 10% of the time. a) Estimate the percent of time "p" that a line between the first and the second stage is busy. How do "n" and "k" affect "p"? How does this "p" affect the blocking performance of the intermediate crossbar switch? b) For a given input and output line, what is the probability that none of the N/n paths between the input and output lines are available? 3. Design a shared memory switching system that supports a time-multiplexed input of 16 channels. Each channel consists of 512 Bytes. The input "frame" duration is 0.4 µsec. The memory (RAM) is organized in 32-bit words with 2 nsec write-in, 2 nsec read-out time and 1 nsec access time (Controller process) per word. 2. What is the minimum required size of the RAM (in Bits) 3. What is the size of a RAM address? 4. What is the throughput (maximum bit rate) of the switch? 5. What is the switching speed (defined as the packet processing rate per second per channel) 4. What is "K" in the Knockout switch refers to? Consider a Knockout switch with the number of inputs N = 8 and the load on the switch is ρ is 0.9 a) What is the minimum value of "K" such that the cell loss rate is less than 10-7? b) What is the minimum value of "K" such that satisfies probability of loss less than 10-5?25. Consider a cell switch positioned at the interface between a customer’s site and a public ATM network. The switch has four OC-3 (An OC-3 link is 155.52 Mbps) SONET/ATM bi-directional links on the customer’s side and one OC-12 (an OC-12 is 622.08 Mbps) SONET/ATM bi-directional link on the public-network side. The OC-3 links have a raw utilization of 50% flowing from the customer towards the public network. The OC-12 link has a raw utilization of 70% flowing from the network towards the customers, and this traffic is distributed evenly among the four customer-side interfaces. Assume that the time to switch a cell is insignificant. All cell streams arrive according to a Poisson process. a) What is the slot time and mean cell delay at the customer-side interfaces? Express your answer in seconds. b) What is the slot time and mean cell delay at the network-side interface? Express your answer in seconds. c) What is the overall mean cell delay of the switch in seconds? Express your answer in seconds. Hint: For the mean cell delay, you need first to decide whether the model is M/M/1 or M/D/1 and then use the appropriate equation from Table 8.6, Stalling's book (this is the material from EE465) 6. Design an NxN STS switch and specify the conditions for which the switch becomes a non-blocking switch. Follow the same argument we did in class for the TST switch. Clearly identify the number of modules in each stage and the definition of the parameters "n" and "k". 7. A shared buffer switch is built from RAM with an access speed of 1 µsec. Suppose the RAM is organized in 16-bit words and the cells are 48 bytes long. What is the throughput of the switch? If this is a 4x4 ATM switch, what is the maximum line rate the switch can handle? ATM Switch OC-12OC-3 Customer Network Public