EE555: "Broadband Networks Architecture" Professor A. Zahid, FALL Semester 2007 HW#3: Solution (Problem 1: 15pts) (Problem 2: 10pts)(Problem 3: 15pts) Problem 3: (Problem 4: 15pts)(Problem 5: 15pts)(Problem 6: 15pts) Problem 6: (Problem 7: 15pts) Problem 7: Assume we have a NxN shared memory ATM switch. Let the input line rate be L cells/sec (equivalently the input line data rate is 48*8*L bits/sec) which means that the input line operates on each cell for 1/L seconds. Since a shared memory switch must read cells in from all lines in one cell time and then read them out, distributing them over the N-output lines, the switching rate (not the throughput) must be 2NL cells/sec. The aggregate throughput is NL cells/sec. Since our RAM is organized into 16-bit words (2 Bytes) and given that each cell is 48 bytes (ignoring the header), the switch through put is 1M/24 cells/sec (since it will take 24µsec to write a cell and 24µsec to read a cell). For the case N=4, the line rate is 1M/(24*4) cells/sec or