Chapter 3 Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow 3 1 Introduction Arithmetic for Computers Floating point real numbers Representation and operations Chapter 3 Arithmetic for Computers 2 3 2 Addition and Subtraction Integer Addition Example 7 6 Overflow if result out of range Adding ve and ve operands no overflow Adding two ve operands Overflow if result sign is 1 Adding two ve operands Overflow if result sign is 0 Chapter 3 Arithmetic for Computers 3 Integer Subtraction Add negation of second operand Example 7 6 7 6 7 6 1 0000 0000 0000 0111 1111 1111 1111 1010 0000 0000 0000 0001 Overflow if result out of range Subtracting two ve or two ve operands no overflow Subtracting ve from ve operand Overflow if result sign is 0 Subtracting ve from ve operand Overflow if result sign is 1 Chapter 3 Arithmetic for Computers 4 Dealing with Overflow Some languages e g C ignore overflow Use MIPS addu addui subu instructions Other languages e g Ada Fortran require raising an exception Use MIPS add addi sub instructions On overflow invoke exception handler Save PC in exception program counter EPC register Jump to predefined handler address mfc0 move from coprocessor reg instruction can retrieve EPC value to return after corrective action Chapter 3 Arithmetic for Computers 5 Arithmetic Logic Unit Design Instruction Fetch ALU operation Instruction Decode Operand a Fetch ALU Execute Result Store Zero Result Overflow b Next Instruction CarryOut Reinman 4 6 One Bit ALU Performs AND OR and ADD on 1 bit operands components AND gate Operation CarryIn a 0 OR gate 1 bit adder Multiplexor 1 Result 2 b CarryOut Reinman 4 7 One Bit Full Adder Also known as a 3 2 adder Half Adder CarryIn a no CarryIn Sum b Inputs Outputs Sum Comments 0 0 0 0 0 00 1 0 1 0 0 1 01 1 0 0 1 0 1 0 01 0 1 1 1 0 0 1 1 10 1 0 0 0 1 1 0 0 01 1 0 1 1 0 1 0 1 10 1 1 0 1 0 1 0 1 10 1 1 1 1 1 1 1 1 11 a b CarryIn CarryOut 0 0 0 0 0 0 CarryOut Reinman 4 8 CarryOut Logic Equation CarryOut a b CarryIn a b CarryIn a b CarryIn a b CarryIn CarryOut b CarryIn a CarryIn a b Inputs Outputs Sum Comments 0 0 0 0 0 00 1 0 1 0 0 1 01 1 0 0 1 0 1 0 01 0 1 1 1 0 0 1 1 10 1 0 0 0 1 1 0 0 01 1 0 1 1 0 1 0 1 10 1 1 0 1 0 1 0 1 10 1 1 1 1 1 1 1 1 11 a b CarryIn CarryOut 0 0 0 0 0 0 Reinman 4 9 Sum Logic Equation Sum a b CarryIn a b CarryIn a b CarryIn a b CarryIn Inputs Outputs Sum Comments 0 0 0 0 0 00 1 0 1 0 0 1 01 1 0 0 1 0 1 0 01 0 1 1 1 0 0 1 1 10 1 0 0 0 1 1 0 0 01 1 0 1 1 0 1 0 1 10 1 1 0 1 0 1 0 1 10 1 1 1 1 1 1 1 1 11 a b CarryIn CarryOut 0 0 0 0 0 0 Reinman 4 10 Chapter 3 Arithmetic for Computers 32 bit ALU CarryIn Ripple Carry ALU a0 Operation b0 CarryIn a Operation CarryIn ALU0 Result0 CarryOut a1 0 b1 CarryIn ALU1 Result1 CarryOut 1 Result a2 b2 CarryOut 1 bit ALU ALU2 Result2 CarryOut 2 b CarryIn a31 b31 CarryIn ALU31 Result31 32 bit ALU Subtraction Expand our 1 bit ALU to include an inverter Binvert Operation 2 s complement take inverse CarryIn of every bit and add 1 a 0 1 b 0 2 1 CarryOut Result Overflow For N bit ALU Overflow CarryIn N 1 XOR CarryOut N 1 Operation Binvert CarryIn a 0 1 b 0 2 Result XOR 1 CarryOut Most significant N 1 bit ALU Overflow Zero Detection Conditional Branches One big NOR gate Zero ResultN 1 ResultN 2 Result1 Result0 Any non zero result will cause zero detection output to be zero NOR Set On Less Than SLT SLT produces a 1 if rs rt and 0 otherwise all but least significant bit will be 0 how do we set the least significant bit can we use subtraction rs rt 0 set the least significant bit to the sign bit of rs rt New input LESS New output SET SLT Implementation All but MSB Most Significant Bit SLT Implementation Set of MSB is connected to Less of LSB Final ALU You should feel comfortable identifying what signals accomplish add sub and or nor slt Chapter 3 Arithmetic for Computers Can We Make a Faster Adder Worst case delay for N bit Ripple Carry Adder CarryIn 2N gate delays 2 gates per CarryOut N CarryOuts a b CarryOut We will explore the Carry Lookahead Adder Generate Bit i creates new Carry gi Ai Bi Carry Look Ahead C0 Cin A0 B0 G P S C1 G0 C0 P0 A1 B1 G P S A 0 0 1 1 B 0 1 0 1 C out 0 C in C in 1 kill propagate propagate generate G A and B P A xor B C2 G1 G0 P1 C0 P0 P1 A2 B2 G P S C3 G2 G1 P2 G0 P1 P2 C0 P0 P1 P2 A3 B3 G P S G G0 P1 P2 P3 G1 P2 P3 G2 P3 G3 P P0 P1 P2 P3 C4 Partial Carry Lookahead Adder Connect several N bit Lookahead Adders together Four 8 bit carry lookahead adders can form a 32 bit partial carry lookahead adder Generate and Propagate 1 bit adder G0 A0 B0 xor G 1 bit adder G1 A1 B1 xor 1 bit adder P1 G2 A2 B2 P0 xor P2 P 1 bit adder G3 A3 B3 xor P3 G G0 P1 P2 P3 G1 P2 P3 G2 P3 G3 P P0 P1 P2 P3 Hierarchical CLA C L A C0 G P C4 G C0 P 4 bit Adder C8 G G P C0 P P 4 bit Adder C12 G G P G P P C0 P P P 4 bit Adder C16 Generate and Propagate C0 4 bit adder A0 A3 G B0 B3 P 4 bit adder A4 A7 G B4 B7 P 4 bit adder A8 A11 G B8 B11 P 4 bit adder A12 A15 G B12 A15 P C4 C8 C12 Carry Select Adder 0 1 1 bit x 1 bit ALU y ALU Result CarryOut CarryIn