IntroductionRegistersRegister with Parallel LoadRegister Example using the Load Input: Weight SamplerShift RegisterSlide 6Multifunction RegistersSlide 8Multifunction Registers with Separate Control InputsRegister Operation TableRegister Design ProcessRegister Design ExampleSlide 13AddersWhy Adders Aren’t Built Using Standard Combinational Design ProcessAlternative Method to Design an Adder: Imitate Adding by HandSlide 17Half-AdderFull-AdderCarry-Ripple Adder1Introduction•Chapters 2 & 3: Introduced increasingly complex digital building blocks–Gates, multiplexors, decoders, basic registers, and controllers•Controllers good for systems with control inputs/outputs–Control input: Single bit (or just a few), representing environment event or state•e.g., 1 bit representing button pressed–Data input: Multiple bits collectively representing single entity•e.g., 7 bits representing temperature in binary•Need building blocks for data–Datapath components, aka register-transfer-level (RTL) components, store/transform data•Put datapath components together to form a datapath•This chapter introduces numerous datapath components, and simple datapaths–Next chapter will combine controllers and datapaths into “processors”2Registers•Can store data, very common in datapaths•Basic register of Ch 3: Loaded every cycle–Useful for implementing FSM -- stores encoded state–For other uses, may want to load only on certain cyclesCombinationallogicState registers1 s0n1n0xbclkI3 I2 I1 I0Q3 Q2 Q1Q0reg(4)Basic register loads on every clock cycleloadHow extend to only load on certain cycles?aDQDQDQDQI2I3Q2Q3 Q1 Q0I1 I0clk4-bit register3Register with Parallel Load•Add 2x1 mux to front of each flip-flop•Register’s load input selects mux input to pass–Either existing flip-flop value, or new value to load1 0DQQ3I31 0DQQ2I21 0QQ1I11 0DQQ0I0load = 01 02×1DQQ3I3loadload1 0DQQ2I21 0DQQ1I11 0DQQ3I31 0DQQ2I21 0DQQ1I11 0DQQ0I0load = 1(b)(c)(a)1 0DQQ0I0I3 I2 I1 I0Q3 Q2 Q1 Q0D4Register Example using the Load Input: Weight Sampler•Scale has two displays–Present weight–Saved weight–Useful to compare present item with previous item•Use register to store weight–Pressing button causes present weight to be stored in register•Register contents always displayed as “Saved weight,” even when new present weight appearsScaleSaved weightWeight SamplerPresent weightclkbSaveI3 I2 I1 I0Q3 Q2 Q1 Q0load3 pounds0 0 1 10 0 1 13 pounds0 0 1 02 pounds1a5Shift Register•Shift right–Move each bit one position right–Shift in 0 to leftmost bit1 1 0 1Register contentsbefore shift right0 1 1 00Register contentsafter shift rightaQ: Do four right shifts on 1001, showing value after each shiftaA: 1001 (original)0100 0010 0001 0000 shr_in•Implementation: Connect flip-flop output to next flip-flop’s inputa6Shift Register•To allow register to either shift or retain, use 2x1 muxes–shr: 0 means retain, 1 shift–shr_in: value to shift in•May be 0, or 1•Note: Can easily design shift register that shifts left instead1 02×1DQQ31 0DQQ21 0DQQ11 0DQQ0shr=11 02×1DQQ3shrshr_inshrshr_in1 0DQQ21 0DQQ1(b)(c)(a)1 0DQQ0Q3 Q2 Q1 Q07Multifunction Registers•Many registers have multiple functions–Load, shift, clear (load all 0s)–And retain present value, of course•Easily designed using muxes–Just connect each mux input to achieve desired functions1shr_ins03 2 1I30DQQ3Q2 Q1 Q0Q3I2 I1 I0I3Q203 2 1I20DQ0Q13 2 1I10DQ0Q03 2 1I00DQ04×1shr_ins1s0(a)(b)Functions:OperationMaintain present valueParallel loadShift right(unused - let's load 0s)s00101s100118Multifunction Registersshr_inshl_in3 2 1I30DQQ3Q2 Q1 Q0Q3I2 I1 I0I3Q23 2 1I20DQQ13 2 1I10DQQ03 2 1I00DQshl_inshr_ins1s0(a) (b)OperationMaintain present valueParallel loadShift rightShift lefts00101s100119Maintain valueShift leftShift rightShift rightParallel loadParallel loadParallel loadParallel loadNoteOperations0s10111000001001111OutputsInputs010101010011001100001111ldshr shlTruth table for combinational circuitMultifunction Registers with Separate Control InputsMaintain present valueShift leftShift rightShift right – shr has priority over shlParallel loadParallel load – ld has priorityParallel load – ld has priorityParallel load – ld has priorityOperationshlshrld000011110011001101010101Q2 Q1 Q0Q3Q2 Q1 Q0Q3I2 I1 I0I3I2 I1 I0I3s1shr_inshr_inshrshllds0shl_inshl_inaa?combi-nationalcircuitas1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shls0 = ld’*shr’*shl + ld10Register Operation Table•Register operations typically shown using compact version of table–X means same operation whether value is 0 or 1•One X expands to two rows•Two Xs expand to four rows–Put highest priority control input on left to make reduced table simpleMaintain valueShift leftNoteOperations0s10101OutputsInputs010000Shift rightShift right1100011100Parallel loadParallel loadParallel loadParallel load00001111010100111111ldshr shlMaintainvalueShift leftOperationld shr shl010000Parallel loadXX1Shift rightX1011Register Design Process•Can design register with desired operations using simple four-step process12Register Design Example•Desired register operations–Load, shift left, synchronous clear, synchronous setStep 1: Determine mux size5 operations: above, plus maintain present value (don’t forget this one!) --> Use 8x1 muxStep 2: Create mux operation tableStep 3: Connect mux inputsStep 4: Map control linesOperationMaintain present valueParallel loadShift leftSynchronous clearSynchronous setMaintain present valueMaintain present valueMaintain present values001010101s100110011s200001111DQQn7 6 3 2 1In05 41 0s2s1s0fromQn-1OperationMaintain present valueShift leftParallel loadSet to all 1sClear to all 0ss000101s101001s200010shl01XXXld001XXclr00001Inputs Outputsset0001Xaas2 = clr’*sets1 = clr’*set’*ld’*shl + clrs0 = clr’*set’*ld + clr13Register Design ExampleStep 4: Map control linesOperationMaintain present valueShift leftParallel loadSet to all 1sClear to all 0ss000101s101001s200010shl01XXXld001XXclr00001Inputs Outputsset0001Xs2 = clr’*sets1 = clr’*set’*ld’*shl + clrs0 = clr’*set’*ld + clrQ2 Q1 Q0Q3Q2 Q1 Q0Q3I2 I1 I0I3I2 I1 I0I3s1ldshls0shl_inshl_incombi-nationalcircuitsetclrs214Adders•Adds two N-bit binary numbers–2-bit adder: adds two 2-bit numbers, outputs 3-bit result–e.g., 01 + 11 = 100 (1 + 3 = 4)•Can design using combinational design process of Ch 2, but doesn’t work well for reasonable-size N–Why