6.01, Spring Semester, 2008—Exploration 9, Issued: Thursday, April 10 1MASSACHVSETTS INSTITVTE OF TECHNOLOGYDepartment of Electrical Engineering and Computer Science6.01—Introduction to EECS ISpring Semester, 2008Exploration 9, Issued: Thursday, April 10This exploration is due April 24 or 25 in your design lab.Option 1: More abstract circuit specificationsThis part of the exploration is worth 5 out of 10 points. If you plan to do option 2, you should doit instead of option 1. If you do option 1 in isolation first, you are likely to find that your solutioncannot be extended easily to option 2.Solving a circuit this way is a lot easier than using a pencil and paper, but it’s still kind of a painto specify the circuit. We find that we often make mistakes with the signs on the KCL constraints.The fact is that, once we know what the components in the circuit are, and how they’re connectedtogether, the entire circuit is specified. In the language we used for last week’s lab, we could doour job with simpler specifications:c = Circui t ([ Resi stor (ra , ’n1 ’, ’n2 ’) ,Re sistor (rb , ’n4 ’, ’ n1 ’),Re sistor (rd , ’n4 ’, ’ n3 ’),Wire ( ’n4 ’, ’ n2 ’) ,VSrc ( vc , ’ n2 ’, ’ n3 ’)])c. solve (’n3 ’)In this specification, we still have to name the nodes, but not the currents. Then, for each compo-nent, we just specify its value and its terminals. The order of the terminals still has to agree withthe order of the variables in the underlying constraint function.Use the underlying constraint-solving code from this week’s lab to implement a system similar tothe one we used last week. Your solution should:• Provide a convenient way to specify circuits (just saying what the components are and howthey are connected together, but not specifying currents);• Implement resistors, voltage sources, and op-amps;• Make it relatively easy to add new components with linear constraints; and• Display solutions nicely.Exploration 1: Hand in your code and demonstrate it on the example in figure 3 of softwarelab 9.Exploration 2: Explain what someone would have to do to add a new type of component.6.01, Spring Semester, 2008—Exploration 9, Issued: Thursday, April 10 2Option 2: Defining and using new primitivesThis option is quite difficult. It is worth 10 points. You can do it as an alternative to option 1.So far, in all of our circuit sepcification methods, we have been able to define primitives and meansof combining them. We haven’t however, been able to build and use abstractions very effectivelyduring circuit specification. We would like to be able to define the pattern of a voltage divider oran inverting amplifier, and then use it as a component in future circuits we might design.So, your goal in this exploration is to implement a system that will:• Provide a convenient way to specify circuits (just saying what the components are and howthey are connected together);• Implement resistors, voltage sources, and op-amps;• Allow you to take circuits patterns that you have already specified and use them as compo-nents in future circuits; and• Display solutions nicely.Note that there is an important difference between the generic idea of an inverting amplifier ora buffered voltage divider and any particular instance of one. A particular instance has actualvoltages and currents, and you can’t put two copies of the same instance in a circuit.This is a very hard problem that can be approached in several ways. Below, we show you somestructures that we built using our solution to this problem. We provide it here to show you thebasic idea of what we want, and to give you some idea of one way to go about it. But it is notcrucial to approach it this way (for example, you might find it easier or more beautiful to make theprogram more functional and less object-oriented than we have here).# A voltag e divide r with r esist anc e r1 on top and r2 on the bottom .# Needs names of top , middle , and bottom nodes .class Divider ( Cir cu it ):def __init__ (self , r1 , r2 , nHi , nOut , nLo ):# Just make a circuit with two resistors , co nnect ed in the# right wayCirc ui t . __i nit__ ( self , [ Resis tor (r1 , nHi , nOut ) ,Re sistor (r2 , nOut , nLo )])# Two div id ers connected to gether ( in our familia r con fig ura tio n that# doesn ’t divide by 4). Uses all the same resistance , for simpl icity .class D oub leD ivi der ( Circuit ):def __init__ (self , r, vPlus , vOut , vMinus ):# Each new in stance of this ci rcuit will have a di ffere nt# inte rnal node ( the ou tp ut of the first di vider ). So , we# have to generat e a new name for that node each time# through . ( See code for gensym for details ).mi ddleNode = gensym ( ’divider ’)# Now , make a c ircuit with two dividers , conne cted up appropriately .Circ ui t . __i nit__ ( self ,[ Divid er (r , r , vPlus , middleNode , vMinus ),Divi de r (r , r , middleNode , vOut , vMinus )])# A common wiring pattern for an op - amp is a si mp le fol lower6.01, Spring Semester, 2008—Exploration 9, Issued: Thursday, April 10 3class Fol lower ( Circuit ):def __init__ (self , vIn , vOut ):Circ ui t . __i nit__ ( self , [ OpAmp (vIn , vOut , vOut )])# A voltag e divide r with r esist anc e r1 on top and r2 on the bottom .# Needs names of top , middle , and bottom nodes . Output of the divider# is run through a follo wer . This is how we made virtual ground .class B uff ered Div ide r ( Circuit ):def __init__ (self , r1 , r2 , nHi , nOut , nLo ):# Have to ge nerate a name for the node that is the output of# the divider and the input to the follo wermi ddleNode = gensym ( ’divider ’)Circ ui t . __i nit__ ( self , [ Resis tor (r1 , nHi , middleNo de ),Re sistor (r2 , middleNode , nLo ) ,Fo llower ( middleNode , nOut )])# Co nnecting two buffered di viders does actua lly di vide by 4class D o ubl eBuf fere dDiv ide r ( Circu it ):def __init__ (self , r, vPlus , vOut , vMinus ):# Have to ge nerate a name for the node that is the output of# the fi rst divider and the top of the second di vidermi ddleNode = gensym ( ’doubleDivider ’)Circ ui t . __i nit__ ( self ,[ Buffered Div ide r (r , r , vPlus , middleNode , vMinus ),Buffer edD ivi der (r , r, middleNode , vOut , vMinus )])# In verti ng ampl ifier s are a handy pa tt ern . We spe ci fy input and# output nodes , and the mul tipli er we …
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