Bluespec for a Pipelined SMIPSv2 Processor 6 375 Laboratory 2 February 23 2009 The second laboratory assignment is to implement a pipelined SMIPSv2 in Bluespec SystemVerilog As with Lab One your deliverables for this lab are a your working Bluespec code checked into CVS and b written answers to the critical thinking questions The lab is due at the start of class on Friday February 27th Again you may submit your question answers on paper in class or electronically in CVS plain text or PDF only As always you may discuss your design with others in the class but you must turn in your own work The goal of this lab is to familiarize yourself with the Bluespec language and compiler with particular emphasis on scheduling Guarded Atomic Actions For this lab we have decided to impose the following restriction do not use Wires RWires PulseWires or any kind of primitive Wire to complete these assignments We feel that it is important for you to gain insight into what the Bluespec scheduler is doing and why These combinational primitives can muddy the picture and make it difficult to reason about your design After completing this lab you will have a much better understanding of when Wires are and are not appropriate and will be better equipped to use these constructs in your project The SMIPSv2 processor you design in this lab will implement the same ISA as the previous lab but will be a different microarchitecure The major difference between this design and the previous lab is the presence of Instruction and Data caches Even on a cache hit data will not be returned until the following cycle This means that the processor must be split into a 4 stage pipeline as shown in Figure 1 This has several ramifications including a you must correctly detect dependencies and stall the pipeline when they occur b when a branch is mis predicted you should not only kill the instructions which were fetched but also correctly ignore all responses from memory requests these instructions have made c FIFOs must be sized appropriately and have good scheduling properties for your design to achieve high throughput Before proceeding you should do Tutorial 8 GAA to RTL Synthesis using the Bluespec Compiler This will familiarize you with the Bluespec compiler and simulating a simple SMIPSv2 microarchitecture generated from BSV source code Additonally you should understand all the concepts presented in lecture Bluespec Modelling Processors The processor in that example although much simpler than the one presented here will serve as a good starting point for your design As with Lab One you should start with the harness at mit 6 375 lab harnesses lab2 harness tgz Processor Overview The design presented in Figure 1 is mostly straightforward the pcGen stage generates the next instruction address using the PC register and sends it to the instReqQ FIFO It also writes the current PC 4 to the pcQ for use in branch instructions The response from the ICache is placed into the instRespQ FIFO Then the Execute stage takes the response out of the FIFO and performs the operation The result of the execution is placed into the writeback queue wbQ the details of which we will explain in Section If the instruction was a load or a store the memory request is 6 375 Lab Assignment 2 Spring 2009 2 Figure 1 Pipeline Rules for SMIPSv2 Processor placed into the dataReqQ queue The Writeback stage is responsible for taking the final result from the wbQ and the dataRespQ and actually updating the register file For your design you will probably want one rule for each stage so a pcGen execute and writeback rule Plus a rule for dealing with the epoch as we will explain in Section The interaction of these rules will be key so carefully craft their predicates and actions When is it safe to execute the next instruction What actions should the writeback rule perform Careful thought about the intent of each rule will aid you during implementation Stalling the Pipeline One significant part of this assignment is generating the stall signal for the execute stage When is it safe to read the register file and execute the next instruction Essentially this means detecting Read After Write RAW hazards So if our design is executing the following program A addiu r6 r10 1 B xor r4 r5 r6 The processor will eventually reach the following state 6 375 Lab Assignment 2 Spring 2009 3 Instruction B cannot be executed because it reads r6 which is being written by instruction A This means we need to stall until the writeback of A is complete We will implement this using SFIFO a searchable FIFO SFIFO is just like a normal Bluespec FIFO except it has the following interface interface SFIFO type any T search T Standard FIFO methods method Action enq any T data method Action deq method any T first method Action clear New SFIFO methods method Bool find search T searchVal method Bool find2 search T searchVal endinterface Note that SFIFO has two extra methods find and find2 These methods take a datatype parameter the same datatype the FIFO is storing and return a boolean Specifically they return True if the given parameter is present in the FIFO and False otherwise find and find2 have no implicit condition they always ready they will simply return False if the FIFO is empty Why does SFIFO include two methods find and find2 This so you can can search it twice for instructions that have two operands For instance in the above example the execute rule can check if r5 is in the writebackQ using find and r6 using find2 However if the instruction had been xori instead of xor it just would have used find because xori just has one register argument What type should you store in the writeback queue and how should you search it First let us condider what the result of the execute stage should be Well if the instruction was an ALU op then the result should be the destination register and the data to put into it If it was a Load then we need the destination register to put the response from memory into If it was a store then we need to record this fact so we can receive the acknowledgement from memory Finally let s treat the From Host register specially 6 375 Lab Assignment 2 Spring 2009 4 typedef union tagged struct Bit 32 data Rindx dest WB ALU Bit 32 WB Host Rindx WB Load void WB Store WBResult deriving Eq Bits Now you must define what it means to search the fifo by writing a function This function should take an Rindx the thing we re looking for and a WBResult the thing we re searching The
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