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GT ECE 4435 - A Voltage Controlled Amplifier

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A Voltage Controlled Am p lifierIn this circuit, y ou will need an n-channel JFET whic h is to be operated as a voltage vari-able resistor. The lab has a supply of 2N5457 JFETs w hich can be used for the experiment.In general, the JFET drain curren t is given byiD= β (vGS− VTO)2where β is the transconductance parameter and VTOis the threshold voltage (which is neg-ativ e). It will be necessary to know num er ical values for β and VTOfor yo u r JFE T. Th isinformation can be obtained from the curve tracer. Dr. Brewer can assist with this.The object of this experimen t is to assemble and test a voltage controlled ampli fier (V CA)that might be used as a variable gain stage in a comp ressor, a limiter, or a guitar effects box.The variable gain elem ent in the VCA is a JFET operated in its linear or triode region. Thebasic circuit is sho w n in Figure 1. The drain-to-source v oltage of the JFET is labeled vAinthe figure. It is giv en b yvA= vIR2R1+ R2For op-amp circuits powered by ±15 V power supplies, a practical upper limit on thepeak input v oltage migh t be tak en to be 10 V. For the JFET to be operated in its linearregion, its drain-to-source voltage shou ld no t exceed VTO,whereVTOis its thr esh old vo ltage(which is negative for the n-channel JFET). To be on the safe side, the limit migh t be tak ento be VTO/2. Th u s, a design specification for the circuit is|vA|max=10R2R1+ R2≤|VTO|2orR1R2≥20|VTO|− 1W hen the JFE T is pinched off,i.e. whenitisaninfinite resistance, the circuit is to bedesigned so that it has a volta ge gain that is 5% to 10% greater than unit y (in the range of1.05 to 1.10). Th is requires1.05 ≤R3R1+ R2≤ 1.10 orR31.1≤ R1+ R2≤R31.05W hen the JF E T is operated in its linear region, it exhibits a resistance from its drain tosource. Let this be denoted by rds. The gain of the circuit is given b yvOvI= −R3R2rdskR2R1+ rdskR2Let the minim um value of rdsbe denoted by rds(min).Itisgivenbyrds(min)=12β |VTO|At this value, the circuit is to exhibit an attenu ation that is 26 dB (a linear factor of 1/20)lo wer than the gain when the JFET is pinch ed off.ThisconditionrequiresR3R2rds(min)kR2R1+ rds(min)kR2=120R3R2R2R1+ R2or R1=·119rds(min)−1R2¸−11To solve for R1and R2, assume a standard 5% value for R3. Calculate the t wo values ofR2for which·119rds(min)−1R2¸−1+ R2=R31.1and·119rds(min)−1R2¸−1+ R2=R31.05Calculate the corresponding values of R1. Repeat for sev eral 5% standard values of R3un tilvalues for both R1and R2that are closest to standard 5% values are obtained.Figure 1: Basic VCA circuit.Assemble the circuit using a TL071, T L0 81, or LF 351 op amp. Use RA= RB=10kΩ.Apply a sine w a ve to the input and a negativ e dc v oltage to vC. Verify that that gain of thecircuit can be varied bet ween unity and 1/20 by varying vCover the range VTO≤ vC≤ 0.Do not apply a dc v oltage outside this range for the JFET could be damaged, and remem berthat VTOis negative. If you have oscillation problem s, put a small value capacitor (hopefullyno larger than 10 pF to 20 pF) in parallel with R3.Onc e the circu it is operatio na l, apply a triangle wave having a peak voltage of 10 V tovI. Connect the x input to the oscilloscope to vIand the y input to vO. You should observea straigh t line having som e curvature on the oscilloscope whose slope at vI=0can be variedapproximately between −1 and −1/20 by v arying vC. Note and record the curvature in thisline. This curvature adds undesired distortion to the signal whic h is to be eliminated in thenext step.The next step is to linearize the circuit to rem ove the curvature by feeding the v o ltag evA/2 back into the JFET gate. A suitable circuit is shown in Figure 2. The output voltageof A2must be negative to prev ent the flo w of gate current in the JFET. Whe n this is thecase, the gate-to-source v o ltage of the JFET is giv en b yvGS= vAR3R2R6R5− vCR6R4TheresistorsaretobechosensothatvGS=vA2− vC2With R5c ho sen to be some con venien t value (e.g. R5=10kΩ), calculate values for R4andR6.UseR7=10kΩ. Note that there is no curren t through R7when vGS< 0 so that thisresistor has no effect on vGS.Figure 2: Circ uit with the linearization voltag e added to the JFET gate v oltag e.Assemble the circuit in Figure 2 using the values calculated abo ve. Note that vCmustbe positive in this circuit because A2in verts the con trol vo ltage. Perform the same tests asfor the circuit in Figure 2 and record the w aveforms. In the follow ing weeks, the V CA willbe used as the con trol element in a compressor circuit. You should neaten up the circuitso that it occupies no more room on the electronic breadboard than is necessary. This isbecause the circuits to be added will occup y more area than this part of the experimen


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GT ECE 4435 - A Voltage Controlled Amplifier

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