14:332:331 Computer Architecture and Assembly Language Spring 06 Week 4: Addressing Mode, Assembler, LinkerMIPS (SPIM) Assembler SyntaxSPIM supported MIPS directiveSPIM supported MIPS directive (cont’d)Slide 5Branching Far AwayDealing with ConstantsImmediate OperandsHow About Larger Constants?MIPS Addressing ModesAddressing Modes IllustratedDesign PrinciplesReview: MIPS ISA, so farThe Code Translation HierarchyCompilerAssemblerOther Tasks of the AssemblerTypical Object File PiecesMIPS (spim) Memory AllocationProcess that produces an executable fileLinkerLoaderSlide 23331 Week 4.1 Spring 2006 14:332:331Computer Architecture and Assembly LanguageSpring 06Week 4: Addressing Mode, Assembler, Linker[Adapted from Dave Patterson’s UCB CS152 slides andMary Jane Irwin’s PSU CSE331 slides]331 Week 4.2 Spring 2006 MIPS (SPIM) Assembler Syntax Comments begin with #. Everything from # to the end of the line is ignored.Identifiers are a sequence of alphanumeric characters, underbars (_), and dots (.) that do not begin with a number.Labels are declared by putting them at the beginning of a line followed by a colon..dataitem: .word 1.text.global main # Must be globalmain: lw $t0, item331 Week 4.3 Spring 2006 SPIM supported MIPS directive .align n align the next datum on a 2n byte boundary..ascii strstore the string str in mem, but do not null-terminate it..asciiz str store the string str in mem, but null-terminate it..byte b1, …, bn store the n values in successive bytes of memory..data <addr> subsequent items are stored in the data segment. If the optional argument addr is present, subsequent items are stored starting at address addr..double d1,…,dn store the n floating-point double precision numbers in successive memory locations.331 Week 4.4 Spring 2006 SPIM supported MIPS directive (cont’d).extern sym size Declare that the datum stored at sym is size bytes large and is a global label..float f1,…,fn store the n floating-point single precision numbers in successive memory locations..global sym Declare that label sym is global and can be referenced from other files..half h1, …, hn store the n 16-bit quantities in successive memory halfwords..kdata <addr> subsequent items are stored in the kernel data segment. If the optional argument addr is present, subsequent items are stored starting at addr..ktext <addr> Subsequent items are put in the kernel text segment. If the optional argument addr is present, subsequent items are stored starting at addr.331 Week 4.5 Spring 2006 SPIM supported MIPS directive (cont’d).set no at It prevents SPIM from complaining about subsequent instructions that use register $at..set no at It prevents SPIM from complaining about subsequent instructions that use register $at..space n Allocate n bytes of space in the current segment (which must be data segment in SPIM).text <addr> Subsequent items are put in the text segment. If the optional argument addr is present, subsequent items are stored starting at addr..word w1,…,wn store the n 32-bit quantities in successive memory words.331 Week 4.6 Spring 2006 Branching Far AwayWhat if the branch destination is further away than can be captured in 16 bits? beq $s0, $s1, L1331 Week 4.7 Spring 2006 Small constants are used quite frequently (often 50% of operands)e.g., A = A + 5;B = B + 1;C = C - 18;Solutions? Why not?put “typical constants” in memory and load them create hard-wired registers (like $zero) for constants Dealing with ConstantsAllow for MIPS instructions like addi $sp, $sp, 4slti $t0, $t1, 10andi $t0, $t0, 6ori $t0, $t0, 4How do we make this work?331 Week 4.8 Spring 2006 MIPS immediate instructions:addi $sp, $sp, 4 #$sp = $sp + 4 slti $t0, $s2, 15 #$t0 = 1 if $s2<15Machine format:The constant is kept inside the instruction itself!I format – Immediate formatLimits immediate values to the range +215–1 to -215Immediate Operandsop rs rt 16 bit immediateI format8 29 29 410 18 8 15331 Week 4.9 Spring 2006 We'd also like to be able to load a 32 bit constant into a registerMust use two instructions, new "load upper immediate" instructionlui $t0, 1010101010101010Then must get the lower order bits right, i.e., ori $t0, $t0, 1010101010101010How About Larger Constants?16 0 8 101010101010101010101010101010100000000000000000 10101010101010100000000000000000331 Week 4.10 Spring 2006 MIPS Addressing ModesRegister addressing – operand is in a registerBase (displacement) addressing – operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instructionImmediate addressing – operand is a 16-bit constant contained within the instructionPC-relative addressing –instruction address is the sum of the PC and a 16-bit constant contained within the instructionPseudo-direct addressing – instruction address is the 26-bit constant contained within the instruction concatenated with the upper 4 bits of the PC331 Week 4.11 Spring 2006 Addressing Modes Illustrated1. Register addressingop rs rt rd functRegisterword operandop rs rt offset2. Base addressingbase registerMemoryword or byte operand3. Immediate addressingop rs rt operand4. PC-relative addressingop rs rt offsetProgram Counter (PC)Memorybranch destination instruction5. Pseudo-direct addressingop jump addressProgram Counter (PC)Memoryjump destination instruction||331 Week 4.12 Spring 2006 Design PrinciplesSimplicity favors regularityfixed size instructions – 32-bitssmall number of instruction formatsSmaller is fasterlimited instruction setlimited number of registers in register filelimited number of addressing modesGood design demands good compromisesthree instruction formatsMake the common case fastarithmetic operands from the register file (load-store machine)allow instructions to contain immediate operands331 Week 4.13 Spring 2006 Review: MIPS ISA, so farCategory Instr Op Code Example MeaningArithmetic(R & I format)add 0 and 32 add $s1, $s2, $s3 $s1 = $s2 + $s3subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3add immediate 8 addi $s1, $s2, 6 $s1 = $s2 + 6or immediate 13