Very Short Answer:(1) (2) What is the relationship between speculation and power consumption?(2) (2) If you are mainly worried about program size, what type of instruction set would you use? Whatif performance was your primary concern?(3) (1) Which is more effective,dynamic or static branch prediction?(4) (1) Do benchmarks remain valid indefinitely?(5) (2) Issuing multiple instructions per cycle puts tremendous pressure on what twoparts of themachine?(6) (2) In class we mentioned VLIW and Superscalar as twoways to circumvent the Flynn Limit of 1.We also talked about twoother approaches - what were they?(7) (2) Out of Order completion makes supporting what very difficult?(8) (2) Are wire delays or transistors more likely to be the most significant limit on clock frequencyinthe future? Why?-1-(9) (2) What does SMT stand for?(10) (2) Decoupled architectures split a program into twostreams. What are they?(11) (2) What is Amdahl’slaw (in words)?(12) (2) What is the primary difference between Scoreboarding and Tomasulo’salgorithm?Short Answers:(10) (4) Whyare there multiple dies per silicon wafer? Whynot just fabricate one huge die per wafer?(11) (3) Write down the 3-term CPU performance equation developed in class.-2-(12) (3) The book lists several things that limit the amount of achievable ILP.List 3 of them.(13) (4)What is a predicated instruction? What are the advantages to using predicated instructions?When would you not want to use one?(14) (4) What is the definition of a basic block? Whyisthere a desire to create larger ones?-3-(15) (3) There are at least twotypes of control flowchanges that standard dynamic branch predictorshave trouble with. There is a technique that works well for one of these types ... name the twotypesof branches, and the technique used to successfully deal with one of them.(16) (4) Supporting precise interrupts in machines that allowout of order completion is a challenge.Briefly explain why, and give three different techniques that can be used to provide precise inter-rupts.(17) (5) Whyisbranch prediction important? What performance enhancing techniques have made it so?List 3 examples of existing Branch Prediction strategies in order of (average) increasing effec-tiveness.-4-(18) (12) Drawabasic high-levelpicture of what tomasulo’shardware looks like, when the ROB isincluded. (In other words, sketch out all the hardware involved, and howthings are connected.) Theemphasis is on conveying knowledge - do not worry about howpretty it is, but do makesure I canread it and understand what you have done.-5-(10) The contents of the table represent the state of the machine at time 6. Your job is to fill in thetable at time 7.Time = 6Instruction StatusIssue Execute Execute WriteInst Underway Completes ResultInstructionLF F2,34(R3) XX XLoad2MULTF F0,F2,F4 XSUBF F8,F6,F2 XDIVF F10,F0,F6 XADDF F6,F8,F2 XReservation StationsTagName Busy Fm(op) Val.j(Vj) Val.k(Vk) Tag.j(Qj) Tag.k(Qk)Add1 Add/Sub YesSub Mem[] 0Load2Add2 Add/Sub YesAdd 00Add1 Load2Add3 Add/SubMult1 Mult/DivYes Mult 0Reg[F4] Load2Mult2 Mult/DivYes Div0Mem[] Mult1Register StatusF0 F2 F4 F6 F8 F10 12 ... F30Tag.i(Qi) Mult1 Load2 Add2 Add1 Mult2Time = 7Instruction StatusIssue Execute Execute WriteInst Underway Completes ResultInstructionMULTF F0,F2,F4SUBF F8,F6,F2DIVF F10,F0,F6ADDF F6,F8,F2Reservation StationsTagName Busy Fm(op) Val.j(Vj) Val.k(Vk) Tag.j(Qj) Tag.k(Qk)Add1 Add/SubAdd2 Add/SubAdd3 Add/SubMult1 Mult/DivMult2 Mult/DivRegister StatusF0 F2 F4 F6 F8 F10 12 ... F30Tag.i(Qi)-6-(19) (14) Youare giventhe following code sequence:ADDF F1,F1,F4SUBF F2,F2,F1MULTF F2,F2,F3DIVF F1,F3,F1Assume there are 8 logical and 16 physical registers. On the left belowisthe register mapping uponentering the code sequence. Your job is to fill in the mappings after the execution of the DIVFinstruction, including what is on the free list. (Assume that during the execution of this code, noregisters are released - in other words, the free list will be shorter at the end than at the beginning.)BEFORELogical Physical031526384115126177Free Pool: 0,2,4,9,10,13,14,15AFTERLogical Physical01234567Free Pool:Now, rewrite the code sequence belowusing the actual physical register names instead of the logicalones.ADDF P__,P__,P__SUBF P__,P__,P__MULTF P__,P__,P__DIVF P__,P__,P__-7-(20) (6) Suppose floating point instructions are responsible for 50% of the execution time of a particularbenchmark, and the floating point square root (FPSQ) by itself is responsible for 23% of the execu-tion time. Youhav e achoice between speeding up the FPSQ instruction by a factor of 10, or makingall floating point instructions run faster by a factor of 1.65. Which should you do? (Showhow youset up the equations, although you do not need to actually solvethem.)-8-(21) (6) In class, we talked about the cycle by cycle steps that occur on different interrupts. Forexample,here is what happens if there is an illegaloperand interrupt generated by instruction i+1:123456789iIFIDEXMEM WBi+1 IF ID EX MEM WB <- Interrupt detectedi+2 IF ID EX MEM WB <- Instruction Squashedi+3 IF ID EX MEM WB <- Trap Handler fetchedi+4 IF ID EX MEM WBFill out the following table if instruction i+1 experiences a fault in the Mem stage (page fault, forexample):12345678910iIFIDEXMEM WBi+1 IF ID EX MEM WBi+2 IF ID EX MEM WBi+3 IF ID EX MEM WBi+4 IF ID EX MEM WBi+5 IF ID EX MEM WBWhat happens in this case?12345678910iIFIDEXMEM WB <- Data write causes Page Faulti+1 IF ID EX MEM WB <- IllegalOpcodei+2 IF ID EX MEM WBi+3 IF ID EX MEM WBi+4 IF ID EX MEM WBi+5 IF ID EX MEM