Prof. Saman Amarasinghe, MIT. 1 6.189 IAP 2007 MIT6.189 IAP 2007Lecture 1Multicore Programming Primer and Programming CompetitionIntroduction2 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.The “Software Crisis”“To put it quite bluntly: as long as there were no machines, programming was no problem at all; when we had a few weak computers, programming became a mild problem, and now we have gigantic computers, programming has become an equally gigantic problem."-- E. Dijkstra, 1972 Turing Award Lecture3 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.The First Software Crisis● Time Frame: ’60s and ’70s● Problem: Assembly Language Programming Computers could handle larger more complex programs● Needed to get Abstraction and Portability without losing Performance4 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.How Did We Solve the First Software Crisis?● High-level languages for von-Neumann machines FORTRAN and C● Provided “common machine language” for uniprocessorsSingle memory imageSingle flow of controlCommon PropertiesISAFunctional UnitsRegister FileDifferences:5 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.The Second Software Crisis● Time Frame: ’80s and ’90s● Problem: Inability to build and maintain complex and robust applications requiring multi-million lines of code developed by hundreds of programmers Computers could handle larger more complex programs● Needed to get Composability, Malleability and Maintainability High-performance was not an issue Æ left for Moore’s Law6 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.How Did We Solve the Second Software Crisis?● Object Oriented Programming C++, C# and Java● Also… Better tools– Component libraries, Purify  Better software engineering methodology – Design patterns, specification, testing, code reviews7 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.● Solid boundary between Hardware and Software● Programmers don’t have to know anything about the processor High level languages abstract away the processors– Ex: Java bytecode is machine independent  Moore’s law does not require the programmers to know anything about the processors to get good speedups● Programs are oblivious of the processor Æ work on all processors A program written in ’70 using C still works and is much faster today● This abstraction provides a lot of freedom for the programmersToday: Programmers are Oblivious to Processors8 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.The Origins of a Third Crisis● Time Frame: 2005 to 20??● Problem: Sequential performance is left behind by Moore’s law● Needed continuous and reasonable performance improvements  to support new features to support larger datasets● While sustaining portability, malleability and maintainability without unduly increasing complexity faced by the programmer Æ critical to keep-up with the current rate of evolution in software9 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.1101001000100001000001978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 2014 2016Performance (vs. VAX-11/780)25%/year52%/year??%/year8086286386486PentiumP2P3P4ItaniumItanium 2The March to Multicore:Moore’s LawFrom David Patterson1,000,000,000100,00010,0001,000,00010,000,000100,000,000From Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 4th edition, 2006Number of Transistors10 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.The March to Multicore:Uniprocessor Performance (SPECint)Specint20001. 0 010 . 0 010 0 . 0 010 0 0 . 0 010000.0085 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07intel 386intel 486intel pentiumintel pentium 2intel pentium 3intel pentium 4intel itaniumAl pha 21064Al pha 21164Al pha 21264Spar cSuper Spar cSpar c 64MipsHP PAPower PCAMD K6AMD K7AMD x86-6411 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.The March to Multicore:Uniprocessor Performance (SPECint)● General-purpose unicores have stopped historic performance scaling Power consumption Wire delays DRAM access latency Diminishing returns of more instruction-level parallelismFrom David Patterson12 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.Power Consumption (watts)Power110100100085 87 89 91 93 95 97 99 01 03 05 07i ntel 386i ntel 486i ntel penti umi ntel penti um 2i ntel penti um 3i ntel penti um 4i ntel i tani umAl pha 21064Al pha 21164Al pha 21264Spar cSuper Spar cSpar c64MipsHP PAPower PCAMD K6AMD K7AMD x86-6413 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.Power Efficiency (watts/spec)00.10.20.30.40.50.60.71982 1984 1987 1990 1993 1995 1998 2001 2004 2006YearWatts/Specintel 386intel 486intel pentiumintel pentium 2intel pentium 3intel pentium 4intel itaniumAlpha 21064Alpha 21164Alpha 21264SparcSuperSparcSparc64MipsHP PAPower PCAMD K6AMD K7AM D x86-6414 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.Range of a Wire in One Clock Cycle00.020.040.060.080.10.120.140.160.180.20.220.240.260.281996 1998 2000 2002 2004 2006 2008 2010 2012 2014YearProcess (microns)700 MHz1.25 GHz2.1 GHz6 GHz10 GHz13.5 GHz•400 mm2Die• From the SIA Roadmap15 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.DRAM Access Latency● Access times are a speed of light issue● Memory technology is also changing SRAM are getting harder to scale DRAM is no longer cheapest cost/bit● Power efficiency is an issue here as well11001000010000001980198219841986198819901992199419961998200020022004YearPerformanceµProc60%/yr.(2X/1.5yr)DRAM9%/yr.(2X/10 yrs)16 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.Diminishing Returns ● The ’80s: Superscalar expansion  50% per year improvement in performance Transistors applied to implicit parallelism– pipeline processor (10 CPI --> 1 CPI)● The ’90s: The Era of Diminishing Returns Squeaking out the last implicit parallelism– 2-way to 6-way issue, out-of-order issue, branch prediction– 1 CPI --> 0.5 CPI performance below expectations projects delayed & canceled ● The ’00s: The Beginning of the Multicore Era The need for Explicit Parallelism17 6.189 IAP 2007 MITProf. Saman Amarasinghe, MIT.AMD OpteronDual CoreIntel Montecito1.7 Billion transistorsDual Core IA/64Intel TanglewoodDual Core IA/64Intel Pentium Extreme3.2GHz Dual CoreIntel Tejas & JayhawkUnicore (4GHz P4)Intel DempseyDual Core XeonIntel Pentium D(Smithfield)CancelledIntel YonahDual Core MobileIBM Power 6Dual CoreIBM Power 4 and 5Dual