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SJSU EE 166 - 4 bit Gray Code

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4 bit Gray CodeAgendaAbstractIntroductionProject DetailsLongest Path CalculationsSchematicLayoutVerificationPowerPoint PresentationSimulationsSlide 12Cost AnalysisLessons LearnedSummaryAcknowledgements14 bit Gray Code Tejas ShahJoseph C. ChungScott TarkulAdvisor: Dr. David ParentDecember 6, 20042Agenda•Abstract•Introduction–Why 4-bit gray code?–Theory of 4-bit gray code encoder/decoder–Background Information•Summary of Results•Project (Experimental) Details•Results•Cost Analysis•Conclusions3Abstract•Target spec–D Flip Flop additional logic used–200Mhz clock frequency–Within 800x800μm2 area–Power density spec of 23W/cm2•Actual–D Flip Flop, XOR and MUX logic used–>200MHz of clock frequency–8mW of Power –area of 250x150m24Introduction•Create code that changes only 1 bit when counting–Example- (decimal) 5 (binary) 0101 (Gray code) 0111 6 0110 0101–Greatly reduces error for counter processes •Encoding: show the Binary to Gray code conversion.A3 A2 A1 A0 (A3)(A3+A2) (A2+A1) (A1+A0) •0 1 1 0 (Binary)  0 1 0 1 •Decoding: Show the Gray to Binary code conversion.A3 A2 A1 A0 (A3)(A3+A2)(A3+..A1)(A3+..A0) •0 1 0 1 (Gray)  0 1 1 05Project Details•Binary to Gray and Gray to Binary–Uniform cell heights of 24.9 μm–5 XOR gates–2 MUX gates •For decoding (Mux_sel=1) and encoding selection (Mux_sel=0)–9 D-Flip Flops6Longest Path CalculationsLogic Level Gate Cg to Drive #CDNs #CDPs #LNs #LPs WN (H.C) WP (H.C) WN (S) WP (S) WN (L) WP (L) Cg of gate 1 MUX-INV 20 1 1 1 1 1.5 2.58 2.85 4.95 2.85 4.95 6.95 2 Mux-NAND 6.95 6 6 2 2 1.63 2.80 2.85 4.95 2.85 4.95 7.6 3 Mux-INV 7.6 1 1 1 1 1.5 2.58 2.85 4.95 2.85 4.95 6.9 4 XOR-AOI 6.9 6 6 2 2 1.63 2.80 1.5 2.55 1.5 2.55 7.5 5 XOR-INV 7.5 1 1 1 1 1.5 2.58 1.5 2.55 1.5 2.55 6.9 6 XOR-AOI 6.9 6 6 2 2 1.63 2.80 1.5 2.55 1.5 2.55 7.5 7 XOR-INV 7.5 1 1 1 1 1.5 2.58 1.5 2.55 1.5 2.55 6.9 nsnsPHL455.475Note: All widths are in micronsand capacitances in fF7Schematic8Layout9Verification1011Simulations12Simulations13Cost Analysis•Time spent on each phase of project–verifying logic: 1 week–verifying timing: 2 weeks–Layout: 3 weeks–post extracted timing: 2 days14Lessons Learned•Start Flip-flop earlier•Minimize cells widths•When troubleshooting power consumption:–measure the power for each component to focus on the problem15Summary•Our circuit is within spec.–Clock > 200MHz–Area is 250x150m2–The circuit power is 8mW•We learned to master implementing a logic design into layout form•Future:–More compact–More bits16Acknowledgements•Thanks to Cadence Design Systems for the VLSI lab.•Thanks to Synopsys for Software donation.•Thanks to Professor David Parent for your support.•Thanks to all the team members.•Thanks to San Jose State for letting us work for late


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SJSU EE 166 - 4 bit Gray Code

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