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Appears in IEEE TVLSI special issue on low power design February 2001 An Energy Efficient High Performance Deep Submicron Instruction Cache Michael D Powell Se Hyun Yang 1 Babak Falsafi 1 Kaushik Roy and T N Vijaykumar School of Electrical and Computer Engineering Purdue University mdpowell kaushik vijay ecn purdue edu Electrical and Computer Engineering Department Carnegie Mellon University syang babak ece cmu edu http www ece purdue edu icalp Abstract technology increases cost and decreases reliability of products in all segments of computing market from portable systems to high end servers 21 Moreover higher energy dissipation significantly reduces battery life and diminishes the utility of portable systems Deep submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage Lowering the threshold voltage increases leakage energy dissipation due to subthreshold leakage current even when the transistor is not switching Estimates suggest a five fold increase in leakage energy in every future generation In modern microarchitectures much of the leakage energy is dissipated in large on chip cache memory structures with high transistor densities While cache utilization varies both within and across applications modern cache designs are fixed in size resulting in transistor leakage inefficiencies Historically the primary source of energy dissipation in CMOS transistor devices has been the dynamic energy due to charging discharging load capacitances when a device switches Chip designers have relied on scaling down the transistor supply voltage in subsequent generations to reduce this dynamic energy dissipation due to a much larger number of on chip transistors Maintaining high transistor switching speeds however requires a commensurate down scaling of the transistor threshold voltage along with the supply voltage 19 The International Technology Roadmap for Semiconductors 20

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