Physics 111 – BSC Lecture 6 Page 1 of 9 Jim Siegrist Phone: 486-4397 Email: [email protected] Room (at LBL): 50-4055 Advice: Today: lec 6 JFET II lec 7 TH Feb 15 lec 8 TH Feb 22 lec 9 TH Mar 8 Labs 1 & 2 solutions posted in hall. Measurements • How do we find JFET Idrain vs. VDS characterization? Logically: idVDSammeterVgs Allows you to get vgs, then vary VDS while measuring current through JFET. • We’ll do something similar in the lab – measure vgs vs. iD. • To get iD vs. VDS for various vgs, use curve tracer. • Similar tracers very useful for diodes, bipolar, etc • In general, devices fabricated in a particular process have to be characterized, parameters extracted, and used in modeling behavior of the devices. • This is a big industry – we engage in at lab in addition modeling radiation-damaged devices. Instruments & Devices • FETs can also act as resistors ⇒ for VLSI circuit FAB, very important – make caps out of silicon layers with SIO2 between, resistors & transistors from FET. • How is a JFET a resistor? For small signals, looks like a voltage-controller resistor. Look in ‘triode’ region, find DSDvi ⇒Physics 111 – BSC Lecture 6 Page 2 of 9 From last time, ⎥⎥⎦⎤⎢⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛−⎟⎟⎠⎞⎜⎜⎝⎛−⎟⎟⎠⎞⎜⎜⎝⎛−=212PDSPDSPgsDSSDVvVvVvIi Divide through by DSv ⇒ ()⎥⎦⎤⎢⎣⎡−−==2212DSPgsPDSSDSDSDvVvVIRvi • Second term is nonlinear – R depends on v, but for small 0≈DSv & we get a pretty good resistor out of this. • Extend the range of linearity by adding a signal to the gate of 2DSv ⇒ RR Handy – you check – mDSgR1~. So resistance in linear region is the inverse of the transconductance in the saturated region. Concept Voltage Amplifier • Generalize source follower discussion from last time • Use symbol inoutOR For an amplifier: Accepts signal vin and generates output vout Across a load RL, where vout is a magnified or (de-magnified) copy of vin (Linear amp ⇒ amplitude & phase shift are only changes in vout, no ω change. •Physics 111 – BSC Lecture 6 Page 3 of 9 • Voltage gain defined by voltage gain inoutvvvA ≡ (express in dB) viniinioutvoutRL • Transfer characteristic is vout vs. vin: voutvinAv1 • Voltage amps have power gain (contrast: transformer) e.g. power gain ()()()ILPPpowerinputPpowerloadA = ininooiviv= • So, JFET source follower last time has power gain ≈ ∞ because iin is 10–9 Amps iout is mA so ratio ≈ 1012 • Likewise, current gain ivPinoiAAAsoiiA == (Extra power comes from the power supply!) Concept Differential Amplifiers – special version of amp • 2 inputs & output ideally depends only on the difference between the 2 inputs ()2−+Δ−=VVV ⇒ Δ= GVVout where G is the gain of the differential amp. V-V = GVoutDVoutV+Physics 111 – BSC Lecture 6 Page 4 of 9 • Real differential amp depends on the average of the two input signals, ()2mod−++=≡VVVVcecommon ⇒ common mode gain ≡ Gcm « G • Used very commonly in analog circuits to reduce noise at the input – rejects signals ‘in common’ at 2 inputs, only ‘sees’ the difference. • Constructed using a ‘matched pair’ of transistors – ideally, a pair with identical characteristics. Circuit Analysis: Common Mode Gain Discussed in notes, but important, so I’ll repeat. Consider the circuit V-V++VRSAVoutR1V = 2 RADi2iDRDRSRD For common mode gain, cVVV ==−+Physics 111 – BSC Lecture 6 Page 5 of 9 Redraw circuit as VCVC+VRSA2R1V = 2R ADiiDRDRSRD2R1iD+V Identical transistors, VC same on both sides ⇒ both halves of circuit behave the same. R1 splits into 2 resistors of twice the original value ()RiVDA2= We’ll have, using the source-resistance model ()()0212111≈⇒>>++===++=cmDSSDCoutcmmsSSCDoutGRRrRRRvvGgrrRRvRv Circuit Analysis: Differential Gain Response to differential signal VD will be equal & opposite DC current flow (Io) through R1 ⇒ voltage at point A will not change ⇒ Replace common resistor by voltage source of strength R1Io:Physics 111 – BSC Lecture 6 Page 6 of 9 V-V++VRSAVoRI1oRDRSRD Again, use source-resistance model ⇒ SSDoutrRVRv+=Δ So SSDoutrRRVVG+==Δ So, for RD » RS, gain is large JFET Common Source Amplifier IOVinVoutG+15VCDCSRDDSRSRGGi = 0vgsSDgvmgssmall signal model: Want ID ~ 5 mA ⇒ look on characteristics (typical): VDS ~ 10V with Vgs ~ –1.5V ⇒ gm ~ 4 x 10–3 1/Ω No current flowing into the input ⇒ SgsSGSVVVVV −=−=⇒=+ 5.10, or VS = 1.5VPhysics 111 – BSC Lecture 6 Page 7 of 9 Ω=−=Ω===⇒700~55.355.111530055.1mAVmAVVRmAVIVRDDSS Take RG big ⇒ RG ~ 1mΩ Small signal model: ()HzCRSS20~1−, RS out for high ν ⇒ VinVoutRDRGvgsgvmgsrosource1/r = I / V ~ 1/60koDDSΔΔignore Input impedance = RG = 1mΩ Output impedance = ro in parallel with RD ~ RD (small signal) ()()3~70011043−Ω⎟⎠⎞⎜⎝⎛Ω×−=−=−==−DminDinminoutRgvRvgvvgain Circuit Analysis JFET Attenuator VinVout1k25k1k-15VPhysics 111 – BSC Lecture 6 Page 8 of 9 Use small signal source resistance model for the JFET: VinVout1k25k1k-15VrSiD ⇒ SDoutriV ⋅= SSinoutrkrVV+⋅=1 You’ll improve linearity range of this in the lab. A smarter circuit: ‘CASCODE’ loadGG+VRQ1Q2iDSDSD Idea: use second JFET (Q1) to hold constant the drain-source voltage vDS of the current source. Q2 passes Q1’s constant drain current through the load, while holding Q1’s drain at fixed voltage – namely, the vgs that makes Q2 operate at the same current as Q1 ⇒ Q2 shields Q1 from voltage swings at the drain ⇒ Q1 just sits there & makes a constant current For this to work, max current of Q2 (IDSS) must be larger than IDSS of Q1 – have to be able to keep both transistors ‘on’!Physics 111 – BSC Lecture 6 Page 9 of 9 Circuit Example from Lab 6 Notes (important, so I point out) Voltage Amplifier +VRSRDVinVout Use source-resistance small signal model RSRDVinVoutSDrS0V+Vi Note SSinrRvi+= (0V G-S voltage) mSgr1= We don’t care about RD for this so iRvDout−= (as if RD goes to ground) inSSDvrRR+−= So ()SSSDinoutrRRRvvgain