ATransition TableInputOutputThe GAL22V10C: An IntroductionPrepared by: P. David Fisher and Diane T. RoverThis document has the following purposes:1. It reviews some important digital-logic topics previously learned including:1.1. Tri-state buffers1.2. Polarity conventions and terminology1.3. Graphical symbols1.4. Flip flops1.5. Selecting input and output-pin polarities1.6. Programmable logic arrays (PLAs)1.7. State-machine models2. It provides an introduction to the specifications and utility of the GAL22V10C.3. It provides an introduction to the tools needed toprogram the GAL22V10C, including:3.1. The CUPL language and compiler3.2. The CSIM simulator and debugger4. It demonstrates how:4.1. Combinatorial logic designs can be implemented using the GAL22V10C4.2. Sequential state-machine designs can be implemented using the GAL22V10C1 gal_lect_f98.doc1. Tri-state buffers: 2. Polarity Conventions: 1 = H (High Voltage) 0 = L (Low Voltage) “Assert” may be 1 (H) or 0 (L)“Not Asserted” may be 1 (H) or 0 (L)3. Example: A 2-of-4 Decoder2 gal_lect_f98.doc2-of-4DecoderSEL-0SEL-3OEA1A0ENABBCACACABBCABCAABDCTruth TableA B C DX X 0 Z0 0 1 00 1 1 01 0 1 01 1 1 1Positive-Logic ConventionA. Output Enable is “asserted” lowB. The decoder is “enabled” by being asserted lowC. The outputs are asserted lowD. The tow-bit address lines use “positive logic.”E. The above logic function can be drawn as follows:F. This decoder is said to be a “combinatorial” logic element.4. The D- type flip flop (latch).3 gal_lect_f98.docD - FFSPDQCLKARQ2-of-4DecoderSEL-3..0OEA1..0ENAB24Transition TablePresentInputNextOutputDnQn+1 = DnA.B. The flip flop is positive-edge triggeredC. The flip flop has an “asynchronous reset” (AR) which is positively asserted.D. The flip flop has a “synchronous preset” (SP) which is positively asserted.5. Selecting Input and Output PolaritiesInput OutputIf P=0, A is selected.If P=1, A is selected.4 gal_lect_f98.docPAA or AA or APA6. The Programmable Logic Array (PLA)A = A0..k-1 B = B0..n-1A is the input data word (k independent variables.) B is the output data word (n independent variables.)B = f(A) in Sum-of-Products form.Examples: B0=A1'A0' + A3'A1A0B1=A3B2=A1'A0 + A1A0'B3=A1 + A2 +A4 + A6We often say that the PLA is composed of two planes: the AND plane and the OR plane. The AND plane forms the “product terms;” the OR plane forms the “sum-of-products.”5 gal_lect_f98.docnBkAPLAOr(Array)6 gal_lect_f98.docNon-Registered OutputsCombinatorialLogicStorageRegistersRegisteredOutputsState BitsLogical Device’s State – Machine Model (See Page 215 in CUPL Manual.)7 gal_lect_f98.doc8. Fisher-Rover State-Machine Model(Tuned for Generic Array Logic – GAL)Note: Input Buffers and Ouput Buffers are not shown.Q3=f3(Sn,I) Mealy MachineNext State Sn+1ARState RegisterCLKSPCL#2II ICL#1Q1=f1(I) Combinatorial OutputInternalResourceControlSnCL#4CL = Combinatorial LogicNext State = Sn+1 = g(Sn, I)SnPresentStateCL#5Q2=f2(Sn)MooreMachineISnCL#3Input (I)Active LowS0 = 0S1 = 1Active HighS0 = 1S1 = 1Combinatorial Mode8 gal_lect_f98.docDA RQQS PC L KActive HighS0 = !S1 = =0DA RQQS PC L KActive LowS0 = 0S1 = =0Registered Mode9 gal_lect_f98.doc1. Coin-Sorter DemoFunctional RequirementsA combinatorial logic circuit must be designed andimplemented using a GAL22V10C to meet thefollowing functional specifications:1. There are five input pins (d, n, oe2, !oe1, andoe0) and three output pins (Q2, Q1, and Q0).2. The “d” input represents a dime.3. The “n” input represents a nickel.4. The remaining three inputs (oe2, !oe1, and oe0)control the tri-state logic for outputs Q2, Q1,and Q0, respectively.5. Q2 is asserted if a nickel and a dime are present.6. Q1 is asserted if a nickel or a dime are present.7. Q0 is asserted if a nickel is present but not adime.10 gal_lect_f98.docName Demo for a GAL22V10C (DIP);Partno Demo_01;Revision 01;Date 7/14/98;Designer P. David Fisher;Company Spartan Embedded Technologies @ Michigan State University;Assembly Prototype;Location 3230 EB;Device GAL22V10C (DIP);/**********************************************************************//* This *.pld file demonstrates the use of basic logic equations in *//* describing the I/O behavior of a combinatorial logic circuit. *//**********************************************************************//** Allowable Target Device--GAL22V10C (DIP) **************************//** Inputs ************************************************************/Pin 4 = d; /* Dime */Pin 5 = n; /* Nickel */ Pin 11 = oe2; /* Tri-state output enable */Pin 10 = !oe1; /* Tri-state output enable (Note negative logic) */Pin 9 = oe0; /* Tri-state output enable *//** Outputs ***********************************************************/Pin 16 = Q2; /* Nickel and dime */Pin 15 = Q1; /* Nickel or dime */Pin 14 = Q0; /* Nickel and not dime *//** Declarations and Intermediate Variable Definitions--None used *****//** State Description for Mealy Machine--None used ********************//** State Description for Moore Machine--None used ********************//** Combinatorial I/O Logic Equations and/or Truth Tables *************/Q2 = n & d; /* Nickel and dime */ Q1 = n # d; /* Nickel or dime */Q0 = n & !d; /* Nickel and not dime *//** Logic Equations for Dynamically Configuring PLD *******************/Q2.oe = oe2; /* Tri-state output enable */Q1.oe = oe1; /* Tri-state output enable */Q0.oe = oe0; /* Tri-state output enable */11 gal_lect_f98.docName Demo for a GAL22V10C (DIP);Partno Demo_01;Revision 01;Date 7/14/98;Designer P. David Fisher;Company Spartan Embedded Technologies @ Michigan State University;Assembly Prototype;Location 3230 EB;Device GAL22V10C (DIP);/**********************************************************************//* This *.pld file demonstrates the use of basic logic equations in *//* describing the I/O behavior of a combinatorial logic circuit. *//**********************************************************************//** Allowable Target Device--GAL22V10C (DIP) **************************/Order: n, %2, d, %2, oe2, %2, !oe1, %2, oe0, %4, Q2, %2, Q1, %2, Q0 ;Vectors:$msg " ! ";$msg " n d o o o Q Q Q";$msg " e e e 2 1 0";$msg " 2 1 0
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