82573LChicken-and-Egg?How ‘transmit’ worksRegisters’ NamesTx-Desc Ring-BufferTx-Descriptor Control (0x3828)Transmit Control (0x0400)Tx Configuration Word (0x0178)Legacy Tx-Descriptor LayoutSuggested C syntaxTxDesc Command-fieldTxDesc Status fieldBit-mask definitionsAllocating kernel-memoryNetwork MTUSingle page-frame optionAnother design-option…InitializationSlide 19Slide 20Extended Control (0x0018)ExampleInterrupt Cause Read (0x00C0)In-Class Exercise #1In-Class Exercise #282573LInitializing our Pro/1000Chicken-and-Egg?•We want to create a Linux Kernel Module that can serve application-programs as a character-mode device-driver for our NIC•So, as with the UART device, we will need to implement ‘read()’ and ‘write()’ methods•But which method should we do first? •No way to “test” a ‘read()’ method without having a way to send packets to our NICHow ‘transmit’ worksdescriptor0descriptor1descriptor2descriptor30000Buffer0Buffer1Buffer2Buffer3List of Buffer-DescriptorsWe setup each data-packets that we want to be transmitted in a ‘Buffer’ area in ramWe also create a list of buffer-descriptors and inform the NIC of its location and sizeThen, when ready, we tell the NIC to ‘Go!’ (i.e., start transmitting), but let us know when these transmissions are ‘Done’Random Access MemoryRegisters’ NamesMemory-information registers TDBA(L/H) = Transmit-Descriptor Base-Address Low/High (64-bits) TDLEN = Transmit-Descriptor array Length TDH = Transmit-Descriptor Head TDT = Transmit-Descriptor TailTransmit-engine control registers TXDCTL = Transmit-Descriptor Control Register TCTL = Transmit Control RegisterNotification timing registers TIDV = Transmit Interrupt Delay ValueTADV = Transmit-interrupt Absolute Delay ValueTx-Desc Ring-BufferCircular buffer (128-bytes minimum) TDBA base-address TDLEN (in bytes)TDH (head)TDT (tail)= owned by hardware (nic)= owned by software (cpu)0x000x100x200x300x400x500x600x700x80Tx-Descriptor Control (0x3828)0 0 0 0 0 0 0GRAN0 0WTHRESH(Writeback Threshold)0 0 0FRCDPLXFRCSPD0HTHRESH(Host Threshold)ILOS0 0ASDE0LRST0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16PTHRESH(Prefetch Threshold)0 0Recommended for 82573: 0x01010000 (GRAN=1, WTHRESH=1) “This register controls the fetching and write back of transmit descriptors. The three threshhold values are used to determine when descriptors are read from, and written to, host memory. Their values can be in units of cache lines or of descriptors (each descriptor is 16 bytes), based on the value of the GRAN bit (0=cache lines, 1=descriptors). When GRAN = 1, all descriptors are written back (even if not requested).” --Intel manualTransmit Control (0x0400)R=0R=0R=0MULR TXCSCMTUNORTXRTLCR=0SWXOFFCOLD (upper 6-bits)(COLLISION DISTANCE)COLD (lower 4-bits)(COLLISION DISTANCE)0 ASDVILOSSLUTBImodePSP0 0R=0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R=0EN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16SPEEDCT(COLLISION THRESHOLD)EN = Transmit Enable SWXOFF = Software XOFF TransmissionPSP = Pad Short Packets RLTC = Retransmit on Late CollisionCT = Collision Threshold (=0xF) UNORTX = Underrun No Re-TransmitCOLD = Collision Distance (=0x3F) TXCSCMT = TxDescriptor Minimum ThresholdMULR = Multiple Request Support82573LTx Configuration Word (0x0178)82573LANETxConfigITCER=0IAMER=0DFPARENPBPARENTxLSTxLSFlow=0R=0PhyPwrDownEnDMADynGER=0RODISReserved(=0)SPDBYPSR=0EERSTASDCHKR=0R=0R=0R=0R=0R=0R=0R=00 0TxConfigWord 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ANE = Auto-Negotiation Enable TxConfig = Transmit Configuration Control bit TxConfigWord = Transmit Configuration Word This register has two meanings, depending on the state of the ANE bit (i.e., setting ANE=1 enables the hardware auto-negotiation machine). Applicable only in SerDes mode; program as 0 for internal-PHY mode.Legacy Tx-Descriptor Layoutspecial0x00x40x80xCCMDBuffer-Address high (bits 63..32)Buffer-Address low (bits 31..0)31 0Packet Length (in bytes)CSOstatusCSSreserved=0Buffer-Address = the packet-buffer’s 64-bit address in physical memory Packet-Length = number of bytes in the data-packet to be transmitted CMD = Command-field CSO/CSS = Checksum Offset/Start (in bytes) STA = Status-fieldSuggested C syntax typedef struct {unsigned long long base_addr;unsigned short pkt_length;unsigned char cksum_off;unsigned char desc_cmd;unsigned char desc_stat;unsigned char cksum_org;unsigned short special;} tx_descriptor;TxDesc Command-fieldIDE VLE DEXTreserved=0RS IC IFCS EOP7 6 5 4 3 2 1 0 EOP = End Of Packet (1=yes, 0=no) IFCS = Insert Frame CheckSum (1=yes, 0=no) – provided EOP is set IC = Insert CheckSum (1=yes, 0=no) as indicated by CSO/CSS fields RS = Report Status (1=yes, 0=no) DEXT = Descriptor Extension (1=yes, 0=no) use ‘0’ for Legacy-Mode VLE = VLAN-Packet Enable (1=yes, 0=no) – provided EOP is set IDE = Interrupt-Delay Enable (1=yes, 0=no)TxDesc Status fieldreserved=0LC EC DD 3 2 1 0 DD = Descriptor Done this bit is written back after the NIC processes the descriptor provided the descriptor’s RS-bit was set (i.e., Report Status)EC = Excess Collisions indicates that the packet has experienced more than the maximum number of excessive collisions (as defined by the TCTL.CT field) and therefore was not transmitted. (This bit is meaningful only in HALF-DUPLEX mode.)LC = Late Collision indicates that Late Collision has occurred while operating in HALF-DUPLEX mode. Note that the collision window size is dependent on the SPEED: 64-bytes for 10/100-MBps, or 512-bytes for 1000-Mbps.Bit-mask definitions enum { DD = (1<<0), // Descriptor DoneEC = (1<<1), //