PSoC 3 PSoC 5 101 Architecture Overview Introduction to PSoC 3 PSoC 5 Workshop Rev H 1 Section Objectives Objectives you will Understand the high level architecture of PSoC 3 PSoC 5 Understand the CPU Digital Analog Programmable Routing Interconnect Subsystems Introduction to PSoC 3 PSoC 5 Workshop Rev H 2 PSoC 3 PSoC 5 Platform Architecture Introduction to PSoC 3 PSoC 5 Workshop Rev H 3 CPU Subsystem ARM Cortex M3 Industry s leading embedded CPU company Broad support for middleware and applications Up to 80 MHz 100 DMIPS Enhanced v7 ARM architecture Thumb2 Instruction Set 16 and 32 bit Instructions no mode switching 32 bit ALU Hardware multiply and divide Single cycle 3 stage pipeline Harvard architecture 8051 Broad base of existing code and support Up to 67 MHz 33 MIPS Single cycle instruction execution Introduction to PSoC 3 PSoC 5 Workshop Rev H 4 CPU Subsystem High Performance Memory Flash memory with ECC High ratio of SRAM to flash EEPROM Powerful DMA Engine 24 Channel Direct Memory Access Access to all Digital and Analog Peripherals CPU and DMA simultaneous access to independent SRAM blocks On Chip Debug and Trace Industry standard JTAG SWD Serial Wire Debug On chip trace NO MORE ICE Introduction to PSoC 3 PSoC 5 Workshop Rev H 5 CPU Subsystem Clocking System Many Clock Sources Internal Main Oscillator External clock crystal input External clock oscillator inputs Clock doubler output Internal low speed oscillator External 32 kHZ crystal input Dedicated 48 MHz USB clock PLL output 16 bit Clock Dividers 8 Digital 4 Analog PSoC Creator Configuration Wizard PSoC Creator auto derive clocking source dividers Introduction to PSoC 3 PSoC 5 Workshop Rev H 6 CPU Subsystem Dedicated Communication Peripherals Full Speed USB device 8 bidirectional data end points 1 control end point No external crystal required Drivers in PSoC Creator for HID class devices Full CAN 2 0b 16 RX buffers and 8 TX buffers I2C master or slave Data rate up to 400 kbps Additional I2C slaves may be implemented in UDB array New peripherals will be added as family members are added to the platform Ethernet HS USB USB Host Introduction to PSoC 3 PSoC 5 Workshop Rev H 7 CPU Subsystem Power Management Industry s Widest Operating Voltage 0 5V to 5 5V with full analog digital capability High Performance at 0 5V PSoC 3 67 MHz PSoC 5 72 MHz 3 Power Modes Active Sleep and Hibernate Introduction to PSoC 3 PSoC 5 Workshop Rev H 8 Designed for Low Power Low Voltage On board DMA Controller Highly configurable clock tree Direct memory transfer between peripherals offloads CPU operation lowering power consumption Flexible automated clock gating Universal Digital Blocks Implement features in hardware that reduce CPU processing requirements lowering power consumption Cached Operations Execution from flash memory is improved by caching instructions PSoC 5 only Precise CPU frequencies PLL allows 4 032 different frequencies tunable power consumption Integrated Analog Digital and Communication Peripherals Reduce external component counts and lower overall system power consumption Introduction to PSoC 3 PSoC 5 Workshop Rev H 9 Low Power Modes Power mode Current PSoC 3 Current PSoC 5 Active 1 2 mA 6MHz 2 mA 6MHz Digital Code resources execution available Yes All Sleep 1 uA 2 uA No I2C Hibernate 200 nA 300 nA No None Analog resources available Clock sources available Wakeup sources Reset sources All All N A All IO I2C RTC Low Speed and Comparator 32 kHz Osc sleep timer comparator None None IO XRES LVD WDR XRES LVD Power Management Enabled in PSoC Creator Provides easy to use control APIs for quick power management Allows code and register manipulation for in depth control Introduction to PSoC 3 PSoC 5 Workshop Rev H 10 Digital Subsystem Universal Digital Block Array UDBs Flexibility of a PLD integrated with a CPU Provides hardware capability to implement components from a rich library of pre built documented and characterized components in PSoC Creator PSoC Creator will synthesize place and route components automatically 32 bit PWM GP Logic 16 bit PWM GP Logic UART 3 GP Logic Fine configuration granularity enables high silicon utilization DSI routing mesh allows any function in the UDBs to communicate with any other on chip function GPIO pin with 8 to 32 bit data buses UART 1 GP Logic UART 2 LCD Segment Drive GP Logic I2C Slave 16 bit Shift Reg GP Logic Introduction to PSoC 3 PSoC 5 Workshop Rev H SPI Master 11 Digital Subsystem Optimized 16 bit Timer Counter PWM Blocks Provides nearly all of the features of a UDB based timer counter or PWM PSoC Creator provides easy access to these flexible blocks Each block may be configured as either a full featured 16 bit Timer Counter or PWM Programmable options Clock enable reset capture kill from any pin or digital signal on chip Independent control of terminal count interrupt compare reset enable capture and kill synchronization Plus Configurable to measure pulse widths or periods Buffered PWM with dead band and kill Introduction to PSoC 3 PSoC 5 Workshop Rev H 12 Analog Subsystem Configurable Analog System Flexible Routing All GPIO are Analog Input Output 0 1 Internal Reference Voltage Delta Sigma ADC Up to 20 bit resolution 16 bit at 48 ksps or 12 bit at 192 ksps SAR ADC 12 bit at 1 Msps DACs 8 10 bit resolution current and voltage mode Low Power Comparators Opamps 25 mA output buffers Programmable Analog Blocks Configurable PGA up to x50 Mixer Trans Impedance Amplifier Sample and Hold Digital Filter Block Implement HW IIR and FIR filters CapSense Touch Sensing enabled Introduction to PSoC 3 PSoC 5 Workshop Rev H 13 Programmable Routing Interconnect Input Output System Three types of I O GPIO SIO USBIO Any GPIO to any peripheral routing Wakeup on analog digital or I2C match Programmable slew rate reduces power and noise 8 different configurable drive modes Programmable input threshold capability for SIO Auto and custom lock able routing in PSoC Creator Up to 4 separate I O voltage domains Interface with multiple devices using one PSoC 3 PSoC 5 device Introduction to PSoC 3 PSoC 5 Workshop Rev H 14 PSoC 3 PSoC 5 Platform Architecture Introduction to PSoC 3 PSoC 5 Workshop Rev H 15 Review You should now Understand the high level architecture of PSoC 3 PSoC 5 Understand the CPU Digital Analog Programmable Routing Interconnect Subsystems Introduction to PSoC 3 PSoC 5 Workshop Rev H 16 Lab 101 My First PSoC 3 Digital Design Introduction to PSoC 3 PSoC 5 Workshop Rev H 17 Lab Objectives