Benchmarking of On-Chip Interconnection NetworksDaniel Wiklund, Sumant Sathe, and Dake Liu∗Dept. of Electrical EngineeringLinköping UniversityS-581 83 Linköping, Sweden{danwi,sumant,dake}@isy.liu.seAbstractMore complex on-chip interconnection structures suchas networks on chip emerge today. As the number of inter-connect architectures rises there is a need to do an impartialevaluation of the performance of the interconnect structure.This is important for both the designer of the interconnectas well as for the system designer in order to achieve bestperformance vs. cost tradeoff. The work presented in thispaper describes a method to specify, execute, and evaluatebenchmarks for on-chip interconnects. The benchmarkingmethod uses formal traffic specifications together with ar-chitecture independent constraints to form the benchmarkspecification. This specification is adapted to the simulationflow available for the interconnect and simulated to get thewanted results. The benchmark method is evaluated usingtwo related examples where throughput is the main focus inthe results. These examples show the applicability of themethod.Keywords: Benchmarking, network on chip, simulation.1. IntroductionOne of the key components in contemporary system de-sign is the interconnect structure. The purpose of the in-terconnect is to provide the possibility to communicate be-tween different functional blocks according to the systemspecification. Dependent on the system specification, thisstructure can be anything from a few wires to a full-fledgednetwork, e.g. the Internet. There has been a lot of workin the design and evaluation of the general purpose stylenetworks used between computers and between boards. Incontrast, this paper will only address the interconnect struc-tures that are used inside a single chip. Being limited toon-chip gives certain constraints on the interconnect design.E.g. silicon cost will limit the size of the interconnect com-ponents thus allowing only small buffers and relatively sim-∗This work is supported by the Swedish Foundation for Strategic Re-search (SSF) through the Stringent electronics research center at LinköpingUniversity.ple functionality. Where a component such as a router in acomputer network can occupy an entire 19-inch rack mountbox, the on-chip counterpart has to fit a space smaller than1 mm2[1, 2].The popularity of networks for use on-chip is increas-ing. Many different research projects have been started inthe last few years [1, 3, 4, 5, 6]. As the number of proposednetwork architectures increase there is a growing need forbenchmarking of these networks. This is necessary in orderto assess the relative performance of the different intercon-nect architectures for the applications intended and to findthe bottlenecks in the interconnect systems.The only way to get benchmarking methods that is fairand usable for comparisons is to create rather formal meth-ods for specification of the benchmarking premises. Themethods can not be limited to a specific type of interconnectbut must apply to any type of interconnect structure. This isnecessary in order to assure that the methods in themselvesdo not limit the usability of the results.Section 2 gives an introduction to networks on chip. Sec-tion 3 discusses simulation of interconnect performance.Section 4 introduces some definitions while section 5 de-scribes the benchmarking method. Section 6 discusses abenchmarking example and the associated results. Finally,section 7 concludes the paper.2. Networks on chipThe traditional method for communication on chip is touse either point-to-point links or time-division buses suchas ARM AMBA. These structures have inherent problemswith scalability and flexibility. The point-to-point intercon-nects suffer from severe inflexibility and the only way ofcreate this flexibility is to add more links. A bus is ratherthe opposite. It is flexible in connecting several ports but atthe price of significantly lower performance per port.A way to lower the impact of these problems is to mergethese two opposites into a network structure. This network-on-chip (NoC) will consist of a shared set of links androuters that will give higher scalability than the bus andIPIPIPIPIPIPIPIPIPFigure 1. Typical mesh networklarger flexibility than the point-to-point links. However thefreedom given in design of a network makes choosing theparameters involved a non-trivial task. There are many ma-jor factors to take into account when assessing the perfor-mance of the network. E.g. there are topology, routing al-gorithm, router arity, physical link design, etc.All these options sum up to a vast design space that willyield significant difference in performance between net-work implementations and traffic patterns.The topology is perhaps the most obvious design choice.The 2-d mesh has turned out to be the most popular topol-ogy because of its simplicity. A section of a 2-d mesh canbe found in Fig. 1. The circles in the figure represent thenetwork routers.3. Simulation of interconnect performanceAn useful analytical model of performance for anetwork-style interconnect is difficult (if not impossible) toachieve. This is due to the inherent complexity of the net-work design space and how the traffic patterns affect the net-work performance. The only practical method of assessingthe interconnect performance is through simulations withreal-world traffic [5, 7].Simulations have the inherent drawback of the resultsnot being better than the stimulus used. For a real-worldapplication it is important to extract the appropriate traf-fic model. Without this model it is more or less impossi-ble to tell whether the simulated interconnect will fulfill theperformance specification. Even with an appropriate trafficmodel, comparison of simulation results for different im-plementations are problematic. All parameters in the simu-lations must be strictly controlled to make the comparisonfair.These drawbacks with simulation together give rise tothe question of benchmarking as a method to compare andassess the relative and absolute performance of different ar-chitectures and implementations. We have identified thisneed and addressed it through the development of a bench-marking process for simulation of interconnect structureson-chip.From the above discussion, the importance of bench-marking for evaluation is evident. The main contributionTable 1. Comparison of DSP and NoC benchmarksDSP NoCConstraints · Native precision ·