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SJSU EE 166 - EE-166 Clocks

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1EE-166 ClocksDavid W. ParentSJSU2Setup Time• Setup Time is the minimum required time for a change on D to cause a change on Q and QB of the master latch (90% of VDD or 10% of GND) before the triggering clock edge.• In our Muxed based flip flop this represents two logic levels.• A Set up error means that your logic path’s delay was too long!– Speed Logic UP!3Hold Time• Hold time is the amount of time that the data has to remain stable near the triggering clock edge.• It is defined as positive if it is after the triggering edge.• It is defined as negative if it is before the clock edge.• A hold error means that the data arrived too soon!– Slow logic down!4Clock to D• Clock to D time is the amount of time it takes for Q and QB of the slave to reach their 90%, 10% values after the triggering edge.• It is also the minimum amount of time the Clock has to stay high for a positively edge triggered flip flop, and how long it has to stay low for a negatively edge triggered flip flop.• This time represent two logic levels of out muxedbased flip flop.• If there is this kind of error it means the clock duty cycle has to be adjusted.5Setup VS Hold• Setup and hold are actually the same thing!– Data not arriving at the proper time to the master latch with respect to the triggering edge.• The two different names are given so the designer knows how to fix the timing error.• Setup and Hold errors violate the conditions under which the library timing data was extracted.6Clocking• Clock Phase Delay (latency)•Clock Skew• Clock Rise Time (skew rate)• Sensitivity to parametric variations of– clock skew– clock phase delay– clock rise time7Clock Phase Delay (latency)• All metal lines (or poly-Si lines) have:– a resistance• The longer the line the bigger the resistance– a capacitance• Between the ground place on even another line• The longer the line the larger the resistance– an inductance • At high frequencies even a metal wire has inductance– Any given length of wire will have an RC delay– The RC delay from one end of a wire to the other end is the Clock Phase Delay ALRρ=8Clock Phase Delay (latency)A Metal Line BClock Phase DelayTimeV9Clock Skew• Lines with different path lengths have different clock phase delays• The Clock Skew is the maximum delay (of the longest line) minus the minimum delay (of the shortest line)• The Clock signal has to have a single starting point.10Clock SkewA BClock Generator(PLL)Metal LineC DMetal LineA and B have zero clockskewC and D have zero clockskewA and C have clock skewA and C have clock skewA and D have clock skewB and C have clock skewB and Dh ave clock skew11Fixes for Clock SkewClock Generator(PLL)C DMetal LineA BMetal LineAll delays are equal: NoClock Skew12Fixes for Clock SkewClock Generator(PLL)WastedAreaWastedArea13Fixes For Clock Skew(Can you say trade off?)QDCKQDCKQDCKQDCKThis circuit has clock skewQDCKQDCKQDCKQDCKNow this interconnect hasa longer delayThis circuit has no clockskew.14Clock Rise Time• The faster the clock edge rises the more noise is introduced into the system.• The Rise Time of the clock edge has to be less that the period. (Even ½ the period is too much.)• ¼ the clock period might work• The rise and fall time equations assume zero rise time and fall time so a finite rise and fall time will cause your transistor widths to be larger to meet your specification.15Buffer Clock Trees• How do we power the clock signal?– Wiring oriented• Manipulate the width and length of the wire ( which in effect is the resistance) to control clock delays– Buffer Oriented• Manipulate inverter buffers to manage delay.16Wiring oriented techniquesControl C by addingparallel pathsControl R by makingwidths smaller or largerFat BusBus is so wide that R isalmost zero17Buffer MethodsBuffer Chain18Buffer MethodsClock Power Up Tree19Buffer MethodsClock power up tree withtappered buffers20Wired vs. Buffered• Wiring-oriented solutions are not sensitive to fabrication variations while buffer-oriented solutions are more so.• The construction of wiring-oriented networks require careful analysis and modeling of inter connect networks, while buffered-oriented networks need careful modeling of the buffer• Buffer oriented solutions potentially consume less power• Embedding the buffers into the placement may not be as easy as a wiring oriented solution.21Where do High Frequency Clock Signals Come From?Phase Locked Loops!22Phase Frequency Detector23Charge Pump24Loop Filter25Voltage Controlled Oscillator26Current Starved Inverter and Voltage Inverter27Divide by Circuit28Elmore Delay• The Clock trees at high frequencies appear to be distributed rather than one lumped parameter.• Unfortunately in the NCSU kit the capacitance extraction is lumped.•Rwire=Rsheet(l/w)• For poly is is 23Ω/square M1-M3 .06Ω/square29Elmore Delay Continued• Capacitance is a little tricky because it is measured with respect to some other signal line.AMI06 fro MOSIS website30Line CapacitanceAssuming a width of .9mm for M1 and M2 and 1.5 for M3L is the length of the line.C=(.9*29+61)xL aF for M1C=(.9*14+58)xL af for M2C=(1.5*7+58)xL af for M3Note this gives a lumped parameter!31RC DelayLumpedT-modelDistributedTphl=.69RC32Elmore Delay• Pi unique Path from input node to node i, i=1,2,3,...N• Pij is the Pi in common with Pj∑∑===NjjkDiRkCj11τNeed to learn by example.For a long line τDN=RC/2 which is smaller than the lumped case.33KS adder (Cint?)34Adder Building Block Cells35Black CellsNand, InvChoose between AOI21, Inv NAND2, NAND2(Inv)36Gray CellsChoose between AOI, Inv NAND2, NAND237BuffersInv, Inv38Cell Height and Width• We have been using 30um so far based on experience. We can use design rules.• Looking at layouts we see that the cell widths in AMI06 to be about:7um+(N-1)*2.4umN equal number of inputs39Black Cells are the largest• They need two tracks (cell heights)• They need two widths (regardless of architecture)• Each adder bit will be 2*30u highAOI21=7+(3-1)*2.4INV=7 Total=18.8~20 Total width is 20*240u.40How long is the wire from the buffer on bit zero to the grey on bit 8• We have to cross 4 black cells (the gray cells will actually be a black cell.• Wire length will be 4*40um=160um• Assume Metal3 leads to 11fF.41How long is the wire from the Propagate across adder chain?• We have to cross 8 tracks.• Each track is 60u• 8*60um=320um• Assume Metal2


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