 MOTOROLA INC., 1992 MOTOROLAM68000 FAMILY Programmer’s Reference Manual (Includes CPU32 Instructions)Introduction 1-2 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA 1.1 INTEGER UNIT USER PROGRAMMING MODEL Figure 1-1 illustrates the integer portion of the user programming model. It consists of thefollowing registers: • 16 General-Purpose 32-Bit Registers (D7 – D0, A7 – A0) • 32-Bit Program Counter (PC) • 8-Bit Condition Code Register (CCR) . 1.1.1 Data Registers (D7 – D0) These registers are for bit and bit field (1 – 32 bits), byte (8 bits), word (16 bits), long-word(32 bits), and quad-word (64 bits) operations. They also can be used as index registers. 1.1.2 Address Registers (A7 – A0) These registers can be used as software stack pointers, index registers, or base addressregisters. The base address registers can be used for word and long-word operations.Register A7 is used as a hardware stack pointer during stacking for subroutine calls andexception handling. In the user programming model, A7 refers to the user stack pointer(USP). Figure 1-1. M68000 Family User Programming ModelA0A1A2A3A4A5A6A7 (USP)PCD0D1D2D3D4D5D6D7DATA REGISTERSADDRESS REGISTERSUSER STACK POINTERPROGRAM COUNTERCCRCONDITION CODE REGISTER0153101531071503101531Introduction MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-3 1.1.3 Program Counter The PC contains the address of the instruction currently executing. During instructionexecution and exception processing, the processor automatically increments the contentsor places a new value in the PC. For some addressing modes, the PC can be used as apointer for PC relative addressing. 1.1.4 Condition Code Register Consisting of five bits, the CCR, the status register’s lower byte, is the only portion of thestatus register (SR) available in the user mode. Many integer instructions affect the CCR,indicating the instruction’s result. Program and system control instructions also use certaincombinations of these bits to control program and system flow. The condition codes meettwo criteria: consistency across instructions, uses, and instances and meaningful resultswith no change unless it provides useful information. Consistency across instructions means that all instructions that are special cases of moregeneral instructions affect the condition codes in the same way. Consistency across usesmeans that conditional instructions test the condition codes similarly and provide the sameresults whether a compare, test, or move instruction sets the condition codes. Consistencyacross instances means that all instances of an instruction affect the condition codes in thesame way. The first four bits represent a condition of the result generated by an operation. The fifth bitor the extend bit (X-bit) is an operand for multiprecision computations. The carry bit (C-bit)and the X-bit are separate in the M68000 family to simplify programming techniques that usethem (refer to Table 3-18 as an example). In the instruction set definitions, the CCR isillustrated as follows:X—Extend Set to the value of the C-bit for arithmetic operations; otherwise not affected or set to aspecified result. N—Negative Set if the most significant bit of the result is set; otherwise clear. Z—Zero Set if the result equals zero; otherwise clear. V—Overflow Set if an arithmetic overflow occurs implying that the result cannot be represented in theoperand size; otherwise clear. XNZVCIntroduction 1-4 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA C—Carry Set if a carry out of the most significant bit of the operand occurs for an addition, or if aborrow occurs in a subtraction; otherwise clear. 1.2 FLOATING-POINT UNIT USER PROGRAMMING MODEL The following paragraphs describe the registers for the floating- point unit user programmingmodel. Figure 1-2 illustrates the M68000 family user programming model’s floating-pointportion for the MC68040 and the MC68881/MC68882 floating-point coprocessors. Itcontains the following registers: • 8 Floating-Point Data Registers (FP7 – FP0) • 16-Bit Floating-Point Control Register (FPCR) • 32-Bit Floating-Point Status Register (FPSR) • 32-Bit Floating-Point Instruction Address Register (FPIAR) 1.2.1 Floating-Point Data Registers (FP7 – FP0) These floating-point data registers are analogous to the integer data registers for theM68000 family. They always contain extended- precision numbers. All external operands,despite the data format, are converted to extended-precision values before being used inany calculation or being stored in a floating-point data register. A reset or a null-restoreoperation sets FP7 – FP0 positive, nonsignaling not-a-numbers (NANs). Figure 1-2. M68000 Family Floating-Point Unit User Programming Model79 63 0FP0FP1FP3FP4FP5FP6FP7FP2FLOATING-POINTDATA REGISTERSFPCRFLOATING-POINTCONTROL REGISTERFPSRFLOATING-POINTSTATUS REGISTERFPIARFLOATING-POINTINSTRUCTION ADDRESS REGISTER071531MODECONTROLEXCEPTIONENABLE0EXCEPTIONSTATUSCONDITIONCODEQUOTIENTACCRUEDEXCEPTION071531 23IntroductionMOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-251.7 ORGANIZATION OF DATA IN REGISTERS The following paragraphs describe data organization within the data, address, and controlregisters. 1.7.1 Organization of Integer Data Formats in Registers Each integer data register is 32 bits wide. Byte and word operands occupy the lower 8- and16-bit portions of integer data registers, respectively. Long- word operands occupy the entire32 bits of integer data registers. A data register that is either a source or destination operandonly uses or changes the appropriate lower 8 or 16 bits (in byte or word operations,respectively). The remaining high-order portion does not change and goes unused. Theaddress of the least significant bit (LSB) of a long-word integer is zero, and the MSB is 31.For bit fields, the address of the MSB is zero, and the LSB is the width of the register minusone (the offset). If the width of the register plus the offset is greater than 32, the bit fieldwraps around within the register. Figure 1-18 illustrates the organization of various dataformats in the data registers. An example of a quad word is the product of a 32-bit multiply or the quotient of a 32-bit divideoperation (signed and unsigned). Quad words may be organized in any two integer dataregisters without restrictions on order or pairing. There are no explicit instructions for themanagement of this