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SJSU EE 166 - 4 Bit Arithmetic Logic Unit

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4 BIT Arithmatic and Logic Unit (Fairchild DM74LS181)AgendaAbstractIntroductionALU Block DiagramDesign flowLongest pathLongest path calculationsSchematicLogical OperationsArithmetic OperationsLayoutTransient ResponsePowerCost AnalysisLessons LearnedAcknowledgement14 BIT Arithmatic and Logic Unit(Fairchild DM74LS181)Kunjal ShahRadha DharmanaRutu PandyaVennela Patchala.Advisor: Dr. David, ParentDecember 5, 20052Agenda•Abstract•Introduction–Why–Simple Theory–Back Ground information (Lit Review)•Design Flow•Project (Experimental) Details•Results•Cost Analysis•Lessons Learned•Acknowledgement3AbstractSpecifications of ALU•Load : 25 fF•16 arithmathic functions•16 logical functions• Propagation delay : 5ns•Clock frequency : 200 MHz•Power requirement : 17 mW•Occupied Area : 373 x373um4IntroductionWhy?•The Arithmatic and Logic Unit is a building block of several industrial circuits.•Design consists of different kinds of Arithmatic operations like Ripple carry adder, subtractor, Transfer data.. Logical operations like AND, OR, XOR, INV.•How the ALU is designed and how it works is essential for designing advanced circuits.5ALU Block Diagram6Design flow7Longest path8Longest path calculations9Schematic10Logical Operations11Arithmetic Operations12Layout13DRC Verification14Transient ResponseA=0, B=1, M=1, S=E, F0 =1, F1=F2 = F3 = 0, F =A+B15Power16Cost Analysis•Time spent on each phase of the project–Verifying logic 1 week–Logic reduction 1 week–Transistor sizing 1 week–Layout of individual blocks 2weeks–Integration of blocks 3 days–post extracted timing 1 day17Lessons Learned•The circuit can be used as a building block for 16/32-bit ALU.•Same metal should not be used in both horizontal and vertical direction.18Acknowledgement•Thanks to Cadence Design Systems for the VLSI lab•Thanks to Professor David W. Parent for his


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SJSU EE 166 - 4 Bit Arithmetic Logic Unit

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