Introduction to Sequential Logic DesignSequential SystemsSequential CircuitsDescribing Sequential CircuitsFinite State MachineClock signalsBistable elementAnalog analysisMetastabilityAnother look at MetastabilityWhy all the harping on metastability?Back to the bistable….Slide 13TerminologyNext…Introduction to Sequential Logic DesignBistable elements2Sequential SystemsA combinational system is a system whose outputs depends only upon its current inputs.A sequential system is a system whose output depends on current input and past history of inputs. All systems we have looked at to date have been combinational systems.3Sequential CircuitsOutputs depends on the current inputs and the system’s current state.“State” embodies all the information about the past needed to predict current output based on current input.State variables, one or more bits of information.The state is a collection of state variables whose values at any one time contain all the information about the past necessary to account for the circuit’s future behavior.Herbert Hellerman, Digital Computer Systems Principles4Describing Sequential CircuitsState tableFor each current-state, specify next-states as function of inputsFor each current-state, specify outputs as function of inputsState diagramGraphical version of state tableMore on this next week5Finite State MachineA circuit with n binary state variables has 2n possible states, which is always finite, so sequential circuits are sometimes called Finite-State Machines (FSM). For most sequential circuits, the state changes occur at times specified by a free-running clock signal.Clock is active high: state changes occur ar rising edge, or when the clock is HIGHClock is active low: falling edge, or when LOWFeedback sequential circuit: uses ordinary gates and feedback loops to obtain memory, create build blocks;Clocked synchronous state machine: uses above building blocks to create circuit.6Clock signalsVery important with most sequential circuitsState variables change state at clock edge.7Bistable elementThe simplest sequential circuit, no way to control its state.Two statesOne state variable, say, Q, two possible statesHIGH LOWLOW HIGHLOWHIGHHIGHLOW8Analog analysisAssume pure CMOS thresholds, 5V railTheoretical threshold center is 2.5 V2.5 V2.5 V 2.5 V2.0 V2.0 V 4.8 V2.5 V2.51 V5.0 V 0.0 V0.0 V 5.0 V9MetastabilityMetastability is inherent in any bistable circuitTwo stable points, one metastable point10Another look at Metastability11Why all the harping on metastability?All real systems are subject to itProblems are caused by “asynchronous inputs” that do not meet flip-flop setup and hold times.Details in Chapter-7 flip-flop descriptions and in Section 8.9 (later in course ECE4110).Especially severe in high-speed systems since clock periods are so short, “metastability resolution time” can be longer than one clock period.Many digital designers, products, and companies have been burned by this phenomenon.12Back to the bistable….How to control it?Control inputs13Back to the bistable….How to control it?Control inputsS-R latch14TerminologyA bistable memory device is the generic term for the elements we are studying.Latches and flip-flops (FFs) are the basic building blocks of sequential circuits.latch: bistable memory device with level sensitive triggering (no clock), watches all of its inputs continuously and changes its outputs at any time, independent of a clocking signal.flip-flop: bistable memory device with edge-triggering (with clock), samples its inputs, and changes its output only at times determined by a clocking signal.Warning: some authors use the terminology Flip-Flop and Clocked Flip-Flop instead of latch and Flip-Floplatch, flip-flop more standard15Next…Latches and flip-flopsRead Ch-7.2HW #11 (Last
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