1Compensator Design to Improve Steady-State ErrorUsing Root LocusProf. Guy BealeElectrical and Computer En gineering DepartmentGeorge Mason UniversityFairfax, VirginiaCONTENTSI INTRODUCTION 2II DESIGN PROCEDURE 2II-A Compensator Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2II-B Outline of the Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2II-C Determining the System’s Steady-State Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3II-D Determining the Value of α .......................................... 5II-E Placing the Compensator Zero and Pole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5II-F Resistor and Capacitor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8References 9LIST OF FIGURES1 Root locus and step responses for the uncompensated and lead-compensated systems. . . . . . . . . . . . . . . . 42 Illustration of placing the zero and pole of the special lag compensator to maintain s1as a closed-loop pole. . . 63 Closed-loop step responses for v arious designs of the special lag compensator. . . . . . . . . . . . . . . . . . . . 74 Root locus for the final compensated system with M = 100.............................. 8These notes are lecture notes prepared by Prof. Guy Beale for presentation in ECE 421, Classical Systems and Control Theory, in the Electrical andComputer Engineering Department, George Mason University, Fairfax, VA. Additional notes can be found at: http://teal.gmu.edu/~gbeale/examples.html.2I. INTRODUCTIONThe purpose of compensator design generally is to satisfy both transient and steady-state specifications. In the root locusdesign approach presented here, these two tasks are approached separately. First, the transient performance specifications aresatisfied, using one or more stages of lead (usually) or lag compensation. Once that is accomplished, the steady-state error canbe dealt with if necessary.The terminology that I use for the compensator designed using root locus methods to satisfy the steady-state error specificationis “special” lag compensator. It will always be a lag compensator, and it is “special” in the sense that it has the mission ofreducing steady-state error without having any effect on the transient performance compensation that has already been done.Therefore, this special lag compensator is not supposed to reshape the root locus as would be done to satisfy transientperformance specifications.Conceptually, the design procedure presented here is graphical in nature. Only very simple calculations are needed to designthe special lag compensator, and the procedure can be easily automated in MATLAB along with other compensator designfunctions.The primary references for the procedures described in these notes are [1]–[3]. Other references that contain similar materialare [4]–[11].II. DESIGN PROCEDUREA. Compensator StructureThe basic special lag compensator consists of one pole and one zero. Multiple stages may be used if the required amountof reduction in steady-state error is too large to be accomplished by a single stage. The compensator structure is describedin more detail in the notes1Compensator Design to Improve Transient Performance Using Root Locus. Assuming the circuitimplementation shown in Ogata [3], the transfer function for the special lag compensator isGc_spec_lag(s)=Vout(s)Vin(s)=(s − zc)(s − pc)=αµs−zc+1¶µs−pc+1¶=αµs|zc|+1¶µs|pc|+1¶(1)where the last form of the compensator comes from realizing that the pole and zero of the special lag compensator will be inthe left-half of the s-plane.Two points can be noted about the transfer function in (1). The firstisthatthegainKc=1. This reduces the number ofparameters that must be computed from three to two, and it means that the absolute value of the gain in the second operationalamplifier in the circuit implementation of the compensator will be R4/R3= C2/C1.The second, and more important, point to note is that the steady-state error of the gi ven system (plant and transient-responsecompensator) will be reduced by a factor of α by the special lag compensator. This can be seen by taking the limit ofGc_spec_lag(s) as s → 0. This means that once we know how much the steady-state error must be reduced, we also know theratio of compensator zero to pole.B. Outline of the ProcedureThe following steps outline the procedure that will be used to design the special lag compensator using root locus methods inorder to satisfy steady-state specifications. Prior to carrying out these steps, it is assumed that all transient response specificationshave been satisfied. Compensator design to satisfy those requirements is discussed in separate notes, Compensator Design toImprove Transient Performance Using Root Locus. It is also assumed that at this point in the design the compensated systemhas the correct System Type. Therefore, the only task that remains is to numerically satisfy a steady-state error specificationfor the particular type of reference input signal that corresponds to the System Type.1) Calculate the value of the steady-state error for the system Gc_trans(s)Gp(s), where the transfer function Gc_trans(s)is the compensator designed to satisfy transient performance specifications and adjust the System Type if necessary.2) Calculate the ratio of the actual steady-state error to the desired value for the error. This ratio also becomes the ratioα = zc/pc.3) Design the compensator:a) Place the zero of the special lag compensator to the right of the real-axis projection of the dominant closed-looppole by a factor of 50–100.b) Place the compensator pole to the right of the zero by a factor of α.4) If necessary, choose appropriate resistor and capacitor values to implement the compensator design.1See http://teal.gmu.edu/~gbeale/ece_421/examples_421.htm l3To illustrate the design procedure, the following system model and specifications will be used:Gp(s)=0.375(s +0.8)s(s +0.2)(s +1)(s +1.5)(2)• steady-state error specification for a unit ramp input is ess_specified=0.2;• step response settling time specification is Ts−specified≈ 16 seconds;• step response overshoot specification POspecified≈ 20%.The two transient response specifications can be satisfied by the phase lead compensatorGc_lead(s)=1.5192 (s +0.2)(s +0.6583)(3)Thus, the open-loop forward path