Overview Of LectureTee Network Line ApproximationTee Network RLC “Line”Terminated Tee Network GainTerminated Tee CharacteristicsTee Characteristics, Cont’dTee Network ExampleTee Design Transfer SimulationTee Design Input Z SimulationComments On Design SimulationsPi Network Line ApproximationPi Network RLC “Line”Terminated Pi Network ResponsesPi Network PerformancePi Network Design ExamplePi Magnitude SimulationsPi Network Group DelayPi Network Input ImpedanceComments On Pi Network DesignFour Section CouplerFirst Level Coupler DesignFirst Level SimulationSecond Level EngineeringSecond Level DesignSecond Level SimulationSecond Level Delay ResponsesAssessment: Second Level DesignSecond Level Pulse TransientsPossible Third Level DesignGeneric Pi DesignGeneric Pi StructureQuasi-Distributed AmplifierAmplifier CommentsAmplifier Comments -- Cont’dEE 541Class LectureWeeks 13-14Prof. John Choma, ProfessorDepartment of Electrical Engineering-ElectrophysicsUniversity of Southern CaliforniaUniversity Park; MC: 0271; PHE #604Los Angeles, California 90089-0271213-740-4692 [USC Office]213-740-7581 [USC Fax][email protected] Filter NetworksFall 2006 SemesterUniversity of Southern California Choma: EE 541265Overview Of LectureOverview Of Lecturez Lumped Line Tee Network Pi Network Synergy With Match Terminated Transmission Line CharacteristicsTransfer FunctionImpedance PropertiesBandwidthDelayz Active Line Topology Design Constraints CompensationUniversity of Southern California Choma: EE 541266+−Z(s)/21Z(s)o Z(s)2 Z(s)in Z(s)o Z(s)/21VoVpViVsZ(s)out z Circuitz Question Can A LoadImpedance Be FoundSo That Zin(s) ≡Zo(s),Independent OfZ1(s) & Z2(s)? If Such An Impedance Can Be Determined:Circuit Emulates Match Terminated Transmission LineVi(s) / Vs(s) = 0.5z Answer Input Impedance Required Load Note Output Impedance Is AlsoZo(s) When Source TerminationEquals Load Termination, Zo(s)LoadSource11in 2 o oZ(s) Z(s)Z(s) Z (s) Z (s) Z (s)22=+ +=1o122Z(s)Z (s) Z (s)Z (s) 14Z (s)=+Tee Network Line ApproximationTee Network Line ApproximationUniversity of Southern California Choma: EE 541267z Circuitz Required Load Purely Resistive For ω >> ωlAnd ω < ωh Realizable As Pure Resistance Of Value RoFor ωl<< ω << ωhω >> ωlRequires Large Shunt Resistance, Rω << ωhRequires Small Capacitance For Given Roz Match Terminated Input Port Gain+−Z(s)o Z(s)in Z(s)o VoVpViVsL/2 L/2 RCZ(s)out 12Z(s) sLRZ(s)1sRC==+2loolhs ωsZ(s) R1sωω=++olhoRLCω 1RCω 2LC 2RC====iisV1H(s)V2==Tee Network RLC “Line”Tee Network RLC “Line”University of Southern California Choma: EE 541268doh2T(0) RC LCω== =+−Z(s) Rin o≅VoVpViVsL/2 L/2 RC RoRoZ(s) Rout o≅iisV1H(s)V2=≈z Circuit Frequency ConstraintsInput ImpedanceOutput Impedance Port Gain Constraintz I/O Transfer Function For Ro<< 2R Butterworth Maximally Flat Magnitude, Third Order Lowpass 3-dB Radial Bandwidth Is ωh Zero Frequency Delayoo23shhhV12H(s)Vsss12 2ωωω=≈++ +Terminated Tee Network GainTerminated Tee Network GainUniversity of Southern California Choma: EE 541269pp2shhV12H(s)Vss1ωω=≈+++−Z(s) Rin o≅VoVpViVsL/2 L/2 RC RoRoZ(s) Rout o≅z Performance Metricsz Interstage Transfer Function Not Butterworth MFM Unity Quality Factor (Q) Peaking, Mp, Prevails 3-dB BandwidtholohoRLCω 1RC; R R 2ω 2LC 2RC==>>==()p2Q2M1.1553112Q===−2b22h15111 1 1 1.27222Q 2Q+=− ++− = =ωωTerminated Tee CharacteristicsTerminated Tee CharacteristicsUniversity of Southern California Choma: EE 54127023hh hin2ohhss s12 2 2ωω ωZ(s)Rss12 2ωω  ++ +  =+++−Z(s) Rin o≅VoVpViVsL/2 L/2 RC RoRoZ(s) Rout o≅olohoRLCω 1RC; R R 2ω 2LC 2RC==>>==z Performance Metricsz Driving Point Input Impedance Low FrequenciesPurely ResistiveSeemingly BroadbandResistiveZin(s) = Ro Very High FrequenciesStrictly InductiveZin(s) ≅sRo/ωh= sL/2Evident From Tacit Inspection Of Circuit AboveTee Characteristics, Cont’dTee Characteristics, Cont’dUniversity of Southern California Choma: EE 541271z Performance Specifications Shunt Resistance, R, Is 20 KΩ Termination Resistance, Ro, Is 50 Ω 3-dB Bandwidth, fh, Is10 GHzz Design Calculationsz Resultant Circuit Resistances In Ohms Inductances InPicohenries Capacitance InFemtofarads+−Z(s) 50in ≅VoVpViVs795.820K 636.6 5050Z(s) 50out ≅795.8()hoollddω 2 R C C 636.6 fFR L C L 1.592 nHω 1RC ω 2π 12.50 MHzT (0) LC T (0) 31.83 pSEC⇒⇒⇒========⇒Tee Network ExampleTee Network ExampleUniversity of Southern California Choma: EE 541272Tee Design Transfer SimulationTee Design Transfer Simulation3-db DownUniversity of Southern California Choma: EE 541273Tee Design Input Z SimulationTee Design Input Z SimulationUniversity of Southern California Choma: EE 541274Comments On Design SimulationsComments On Design Simulationsz Transfer Relationships Input/Output Appears To Be Maximally Flat Magnitude Bandwidth Is the 1 GHz Design Objective Gains At Low Frequencies (Both Functions) Are ½ Peaking Evidenced In Interstage Transfer, As Predicted Bandwidth Of Interstage Function Is Larger Than That Of I/O Function, As Expectedz Input Impedance At Low Signal FrequenciesReal Part Is 50 Ohms Up Through About 40% Of BandwidthImaginary Component Is Appears To Be Broadband Zero At High Signal FrequenciesReal Part Component Degenerates To ZeroImaginary Part Component Reflects Inductive Input Impedance Complex Frequency Dependence Causes Non-Monotonic Input Port ResponseUniversity of Southern California Choma: EE 541275z Circuitz Strategy Determine LoadImpedance So ThatZin(s) ≡Zo(s),Independent Of Z1(s) & Z2(s) With Zin(s) ≡Zo(s)Circuit Emulates Match Terminated Transmission LineVi(s) / Vs(s) = 0.5z Result Input Impedance Required Load Note Output Impedance Is Also Zo(s) WhenSource Termination Equals Load