Contains material © Digilent, Inc. 11 pages Lab #8: DFFs and Registers Revised 3_22_10 Overview So far in the class, we have been dealing with combinational circuits – circuits that are only dependent on the present inputs. Now, we begin a new direction in the class, dealing with sequential circuits – circuits that are dependent on the present input as well as the present state. Sequential circuits have memory to remember what has happened in the past. The memory devices that will be designed use latches and flip-flops. Before beginning this module, you should… After completing this module, you should… - Be well practiced in the design of various combinational circuits. - Be familiar with the Xilinx ISE design tool suite. - Understand how latches and flip-flops can store data. - Understand how to implement register - know the schematics and Verilog code for the devices This lab exercise requires: -A Digilab BaSYS board -A PC running the Xilinx WebPack or ISE CAD tools Modules created in this lab: - D-Flipflop with clr - One-bit register with clr - Four-bit registerLab #10 DFFs and Registers Contains material © Digilent, Inc. 2 Introduction We’ve been built combinational circuits which only consider current input. There is another class of logic circuits we will learn. These circuits are two-valued networks in which the outputs at any instant are dependent not only upon the inputs present at that instant but also upon the past history (sequence) of inputs. The block diagram of a sequential circuit is shown below: FIGURE 1 SEQUENTIAL CIRCUIT DIAGRAM The basic logic element that provides memory in many sequential circuits is the flip-flop. Edge triggered D Filpflops The D flip-flop is the most common flip-flop in use today. It is better known as data or delay flip-flop. Below is a diagram of a positive-edge triggered D-FF created using an all NAND implementation. With this diagram, the value of D gets latched, or locked in, at the positive edge of the clock. This is a D FF – an edge sensitive device. FIGURE 2 D-FF NAND IMPLEMENTATIONLab #10 DFFs and Registers Contains material © Digilent, Inc. 3 FIGURE 3(A) D-FF SIMPLIFIED REPRESENTATION (B) TRUTH TABLE The Q output takes on the state of the D input at the moment of a positive edge at the clock pin. It is called the D flip-flop for this reason, since the output takes the value of the D input or data input, and delays it by one clock cycle. The D flip-flop can be interpreted as a primitive memory cell, or delay line. Whenever the clock is at rising edge, the value of Q is D and the previous Q value otherwise. One the table, X is ‘don’t care’ value. Verilog Implementation of D-Flip flop Behavioral model Behavioral model is higher level of modeling where behavior of logic is modeled. Verilog behavioral code is inside procedure blocks, but there is an exception: some behavioral code also exist outside procedure blocks. There are two types of procedural blocks in Verilog: - initial : initial blocks execute only once at time zero (start execution at time zero). - always : always blocks loop to execute over and over again; in other words, as the name suggests, it executes always. Example: initial statement module initial_example(); reg clk,reset,enable,q_in,data; initial begin clk = 0; reset = 0; enable = 0; data = 0; end endmodule Like C like programming, we can set initial values for certain modules. If you want to ‘welcome’ or ‘ready’ messages on the BaSYS board by using LEDs or SSDs (even though SSD has a limitation for representing alphabets)Lab #10 DFFs and Registers Contains material © Digilent, Inc. 4 Example: always statement module always_example(); reg clk,reset,enable,q_in,data; always @ (posedge clk) // this means every time clk is at positive edge if (reset) begin // do these data <= 0; end else if (enable) begin data <= q_in; end endmodule In an always block, when the trigger event occurs, the code inside begin and end is executed; then once again the always block waits for next event triggering. This process of waiting and executing on event is repeated till simulation stops. D-FilpFlop There are several ways to write D-flip flop. Like Figure 2, we can directly implement gate level D-FF. Or we can implement by using behavioral statement. Here we are going to use behavioral statement. Example: D-FlipFlop with clear(reset) module DFF_clr(CLK, CLR, D, Q); input CLK; input CLR; input D; output Q; reg Q; // the output must be assigned in register value, so declare // Everytime CLK or CLR signal is at positive edge (posedge), // do next always @(posedge CLK or posedge CLR) if(CLR == 1) Q <= 0; else Q <= D; endmodule As explained in the example, when the CLK or CLR signal is at positive edge, it executes the statemets ‘if ~else’ statement. ‘posedge’ means positive edge. Usually, the CLK we use is ‘up and down’ 50 M per second or 50 MHz. Therefore, if data (D) comes into this module, it will be assigned on output (Q) in a very short time.Lab #10 DFFs and Registers Contains material © Digilent, Inc. 5 Registers Registers are a storage device for data. Within a computer, registers are used to hold the values that are used by the ALU, as well as the result of the ALU. An m-bit register consists of m edge-triggered flipflops with a common clock. A register has a control line called “load” that is used to load the register with a new value from an external bus. FIGURE 4 REGISTERS IN CPU In the previous examples, we learned that D FFs can be used to store one bit. We want to expand the one-bit FF to a sequential building block – a four-bit register. A register is a storage building block. If D is high at the active edge of the clock, the value of D is stored in the FF. Since the clock in a digital system is very fast, the new value of Q is changed every clock period. To reduce the number of times that the data is entered into the register, we will add a new input called load which is asynchronous to the clk. The diagram below shows the basic model for a register. Notice that the register includes a D flipflop and a 2:1 MUX. Inputs are Din, LD, CLK, and ACLR. Outputs are Dout. FIGURE 5 1-BIT REGISTER DIAGRAMLab #10 DFFs and Registers Contains material © Digilent, Inc. 6 By using hierarchical design,