1166: Design of CMOS Digital Integrated Circuits David W. Parent Assistant Professor Office Hours: MW 11:45am-12:45pm T and F 10:00-11:00am EE Department SJSU PH: 408.924.3963 EM: [email protected] HP: http://www.engr.sjsu.edu/dparent Course Description: Analysis and design of MOS based combinational and sequential digital integrated circuits. Industry standard CAD tools (Cadence) will be used extensively in homework and a group final project. Course Aims: 1. Prepare students to be productive members of an industrial digital circuit design team. 2. Prepare students for graduate study or carry out a senior design project in the VLSI field. 3. Provide an environment where students learn to think critically. 4. Provide an environment where students learn to enjoy the design and learning processes. 5. Have students internalize the culture of the design engineer. Course Objectives (Outcomes): To be productive members of an industrial digital circuit design team students should be able to: • analyze circuits using both analytical and CAD tools • use a design flow to design a CMOS integrated circuit in a team environment. • present results orally • interpret a design specification To be prepared for graduate study in the VLSI area students should be able to: • derive basic analytical MOS circuit equations • locate information not presented in class in the library Students who can think critically can: • design test benches that can prove that a design meet a specification • identify regions where circuit models are valid2 It is my hope that students learn to enjoy the learning/design process through a “hands on” approach to CMOS IC design. Course Topics: 1) Choosing an Architecture (1) 2) Review MOS equations (3) 3) Spice Model (2) 4) CMOS Inverter (1) 5) Delay in a MOS inverter (3) 6) Switch Model (1) 7) Tri-State (1) 8) Stick Diagrams (1) 9) Layout (2) 10) NAND/NOR GATES (1) 11) XOR, AOI (1) 12) Latches (1) 13) Flip Flops (2) 14) Schmitt Triggers (1) 15) Clocking (1) 16) Setup/Hold/Skew (1) 17) Clock Architectures (1) Outcome Assessment (Grading): • Homework (10%): (-20% per day late) Homework will consist of a mix of circuit analysis and design problems. Analytical and CAD based techniques will be required to solve problems. The homework is designed to reinforce lecture concepts and prepare the student for the exams and class project. Homework assignments will be due roughly each week. Students are encouraged to work in groups, but each student needs to try to solve the homework problems, before group meetings. Each homework set will consist of the following: o Derivation of analytical circuit equations o Analysis of circuit performance using analytical equations o Design of digital circuit using analytical equations o Analysis of circuit performance using CDS tools o Design of digital circuit using CDS tools • Exam 1 (17%): Topics 1-5: The first exam will cover topics 1-5. The questions will be based on both circuit/device analysis and design using analytical techniques only (no CAD). This exam will access individual knowledge up to the transient response of a CMOS inverter. The CMOS inverter is the building block for the more advanced circuits to follow.3• Exam 2 (17%): The first exam will cover topics 6-11 The questions will be based on both circuit/device analysis and design using analytical techniques only (no CAD). This exam will access individual knowledge covering combinational logic. • Project (20%):(-20% per day late) The project will be team based with 3-4 people per team. Teams members will be responsible for a 20-transistor sub design each. All groups will use the AMI06 process technology. The project will access the ability to work within a team, interpret a specification; present results orally, locate information not presented in class, and use a design flow. It will indirectly measure the ability to use industry standard CAD tools. All team members will be accessed in the following manner: o The result of the project will be a .5 micron CMOS digital circuit design that has been created according to the CLASS DESIGN FLOW. The circuit performance will be validated with spice and the circuit will be laid out according to SCMOS rules, and ready to be placed within a pad frame. The idea is to have a circuit design ready for a MOSIS FAB RUN. 20%-group grade. o Extra credit can be earned by doing more advanced projects that include concepts not covered in class. o Depending on the effort level of each team member, not all group members will receive the same grade. • Final Exam (36%): The final exam will be the same format as the exams. • Laboratory: Lab experiences will not be graded directly since this course has no associated lab with it. However, the project, which will be conducted primarily in lab, does represent 20% of the total grade. Cadence tutorials and handouts will be provided on line, as well as extra lab sessions where instruction on how to use Cadence tools will be given. Class Schedule: Class DATE TOPICS Comments HW Due Project Items Due 1 1/25/2006 Getting Started, Overview, Physics 2 1/30/2006 Review MOS Equations I 3.3, 3.4 HW1 2/1/2006 Review MOS Equations II 3.5, 3.6 4 2/6/2006 Spice Model I 4.1, 4.2, 4.3 HW2 ID GROUPS 5 2/8/2006 Spice Model II 4.4, 4.5, 4.6 6 2/13/2006 CMOS Inverter 5.1,5.5 7 2/15/2006 LAB DAY Read Chapter 1&2 of Tutorial Start Chapter 3 8 2/20/2006 Delay in a CMOS Inverter I 6.1, 6.2, 6.3 HW3 ID PROJECT49 2/22/2006 Delay in a CMOS Inverter II 6.5, 6.6, 6.7 10 2/27/2006 Midterm #1 Review HW4 FINALIZE SPEC 11 3/1/2006 Midterm #1 12 3/6/2006 Exam Results/Project Management 13 3/8/2006 Processing/Stick/Switch Wolf and Tauber 14 3/13/2006 Layout I 2.1, 2.2, 2.3 15 3/15/2006 Layout II 2.4, 2.5 16 3/20/2006 NAND/NOR 7.3 HW5 PARTS LIST 17 3/22/2006 XOR/AOI/ Project Management 7.4 3/27/2006 spring break 3/29/2006 spring break 18 4/3/2006 FIFO Chip Example 19 4/5/2006 Review HW6 VERIFY LOGIC in NC verilog 20 4/10/2006 Midterm # 2 21 4/12/2006 Latches 8.1, 8.2, 8.3 22 4/17/2006 Flip Flops 8.4/8.5 23 4/19/2006 Clocking, Setup/Hold/Skew, Clock Architectures 13.5, 4.2-4.3 Wong VERIFY FLIP FLOPS and initial Floor Plan 24 4/24/2006 Schmitt Triggers/ Super Buffer Chapter 8 Appendix 25 4/26/2006 Power Grid Layout