Crawley/lf, 3/23/01 1 16.070 Communication, Flip-Flops, A/D, D/A 3/23/01 Lecture #19 16.070 • Introduction ¾Parallel and serial communication ¾Sequential logic Æ flip flops ¾Analog-to-digital and Digital-to-analog conversionsCrawley/lf, 3/23/01 2 16.070 Typical Computer Bus Architecture Fast Local Bus (e.g., PCI)Watchdog TimerVery fast system bussesASRAM CacheprocessorDRAMDhard disk controllerto diskADADgraphics adapterbus bridgeto devicessystem controllerserial portsmodemserial connection (RS232)speakermousekeyboardto Local Networ (e.g., Ethernet)instrument busscopevoltprintertapeCD ROMA/DD/AAnalog inAnalog outInstrument Bus (e.g., IEEE-488/GPIB)Slower Local Parallel Bus e.g., ISA, SCSI)Slower Local Parallel Bus e.g., ISA, SCSI)Crawley/lf, 3/23/01 3 16.070 Notes on Computer Bus Architecture • Very fast address (A) and data (D) system busses connect processor, system controller, static random access memory (SRAM) cache and local Dynamic Random Access Memory (DRAM). These system busses are processor specifics • A fast local bus, controlled by the system controller, connects to very high data rate devices, such as graphics adapters and hard disk controllers • A bus bridge controller hangs on the fast local bus, and controls slower busses ¾A slower parallel bus (e.g., ISA, SCSI) for high bandwidth peripherals ¾A serial link for medium/low bandwidth peripherals • Sometimes the function of the local fast and slower busses are combinedCrawley/lf, 3/23/01 4 16.070 Serial Connections • Typically have 1 or 2 data lines, a few control lines, and ground • Data are sent in a serial stream of bits down the data line • Oldest and most common is RS-232 ¾TD - transmit data: data are sent via this line ¾RD - receive data: data are received here ¾RTS - request to send: set when unit wants to transmit ¾CTS - clear to send: set when ready to receive • Standard RS-232 is 19.6K BPS (~1960 bytes/sec) 3322778855TDRDRTSCTSGNDTDRDRTSCTSGNDCrawley/lf, 3/23/01 5 16.070 RS-232 Timing and Framing − RTS goes high, ready to transmit − CTS goes high, go ahead − Idle (1) drops to 0, a start bit to start the frame. Then the 5, 6, or 7 data bits, LSB Æ MSB, (here ASCII code), then 0 or 1 parity bits, then 1, 1.5, 2 stop bits (in duration) − CTS goes low, as receiver clears buffer (it may or may not depending on how fast the receiver is) − Second data frame starts RTS at transmitterCTS at transmitterT-D at transmitidlestart bit0100000ASCII code "A"11paritystop00000startASCII code "P"1111paritystopCrawley/lf, 3/23/01 6 16.070 Parallel Busses • All parallel busses have in common ¾A parallel set of lines for data ¾A parallel set of lines for address (which in more sophisticated busses may be multiplexed with data) ¾Command lines to indicate when reads and writes should occur, and to signal willingness/not to receive • Parallel busses differ in ¾Mechanical arrangement of pins ¾Number of devices per bus ¾Control by controller/initiator ¾Width (i.e., how many lines) ¾Speed/frequency ¾Parity CheckingCrawley/lf, 3/23/01 7 16.070 Parallel Bus - SCSI • SCSI (Small Computer System Interface) is a daisy-chain parallel bus for up to 7 (or 15) high bandwidth peripherals • Each device has a SCSI address 0-7 of which one is the "host" adapter • No device is always the controller, but at any instant, one device is the initiator, a second the target, and only these two communicate at any one time • The initiator takes control of a quiet bus and requests an action of a target • Communication at 10-20MBPS 2 4 . . . 16 18 32 36 38 40 42 44 46 48 50D0-D7 PARITY ATN BSY ACK RST MSG SEL C/D REQ I/OCrawley/lf, 3/23/01 8 16.070 SCSI Timing and Sequencing • A device takes control of the bus by raising BSY (busy) and its address on D0-D7. This lets all others know it's the initiator (if two try at once, there is arbitration that uses SEL (select)) • The initiator then notifies the target by raising ATN (attention) and the address of the target on D0-D7 • The target raises REQ (request) saying it is ready • The initiator puts the first byte on D0-D7 and raises ACK (acknowledge) • The target reads D0-D7 and drops REQ • The initiator drops ACK BSYATNREQACKD0-D7initiator addresstarget addressData Byte 1Data Byte 2Crawley/lf, 3/23/01 9 16.070 A Third Option - Packetized Data • Parallel busses connect many devices, and use many parallel lines for address, data, and commanding • Serial connections connect two devices, and use 1 or 2 lines for data, and a few for commanding • Packetized data uses only 2 lines (like a serial connection) but can connect many devices ¾Transmitting device creates a serial packet which has a header, which includes its address, and the address of the target ¾Transmitting device waits for quiet line, and puts its packet, serially, on the common line ¾All devices listen for their address in header, copy their packet and (sometimes) acknowledge sender • Various levels of implementation ¾USB (Universal serial bus) to mouse, keyboard, etc. ¾Ethernet in LAN (Local Area Network) in an office ¾TCP/IP (Transmission Control Protocol/Internet Protocol) in the internetCrawley/lf, 3/23/01 10 16.070 Sequential Logic • Up until now, all logic has been combinational - the output is determined completely by the existing state of the inputs. • Sequential Logic creates memory in a set of gates • Simplest is an S-R flip-flop ¾S and R Lo Æ no change − Q = 0, Q = 1 and Q = 1, Q = 0 both allowed ¾S Hi, the output (Q) is Set to 1, regardless of previous state ¾R Hi, the output (Q) is Reset to zero S R Qn+1 0 0 Qn 0 1 0 1 0 1 1 1 indeterm. RSQQCrawley/lf, 3/23/01 11 16.070 Clocked Flip-Flops • Clocked R-S ¾Performs RS function when clock strobes • D Flip-Flop ¾Latches Data line ¾The element of Latch in Static Ram S'R'QQCSRS' R' Qn+10 0 Qn0 1 01 0 01 1 --DQQCSRD Qn+10 01 1Crawley/lf, 3/23/01 12 16.070 J-K Flip-Flops • J-K Flip-Flop ¾Same as S-R except J=1, K=1 "toggles" output • Master-Slave J-K ¾Same as J-K except master flips when clock rises, slave flips when clock drops J K Qn+10 0 Qn0 1 01 0 01 1 QnCrawley/lf, 3/23/01 13 16.070 A Flip-Flop Counter • Output counts from 0 to (15)10 and then resets