TitleSlide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14All Digital Ultra Fast Acquisition PLLProject for ECE 734VLSI Array Structures for DSPAtul Bhadkamkar5/7/2010All Digital PLL➲RF frequency synthesizer is key element in all up-down con-versions of radio/high frequency circuits➲Linear frequency chirp in new 60 GHz radars requires a 3.2 GHz bandwidth in 2 ms sweep➲Range resolution better than 5 cm requires at least 6 GHz sweeping range with linearity better than 0.05 %➲Acquisition time requirements are less than 5 us➲Traditional charge pump based PLLs, generate spurs and hence loop bandwidth is low➲Time to digital converter does not generate spurs and hence digital loop filter bandwidth can be set for optimal perform-ance➲All Digital PLL combines the best of PLL and DFS●Fast switching, high resolution, low power, wide rangePLL Design➲Frequency Range➲Frequency Resolution➲Acquisition Speed – This work concentrates on●Time to settle down to within a specific frequency +/- x Hz from de-sired new frequency●For eg. Commercial handsets: 160 us for GSM, 150 us for WCDMA●10 us for a basestation PLL achieved with large current consumption, larger area and higher complexity➲Phase transient●During switching no transients – eg. in radars, MSK➲Phase Noise●High quality synthesizers have 99.99% of energy within 1 Hz of bandwidth around carrierDesign Simulated➲Frequency range - +/- 50 MHz around carrier➲Frequency step size in Digital Osc. = 50 KHz➲PFDout = 2*round((DivTime-RefTime)/100e-12 – 1●Max. value of 1250, requires 12 bits + 1 sign➲Dcontrol = round(Int + alpha*IIR)●Int(n) = Int(n-1) + err●Max. of Int = Max of err * (1 – a^n) / (1 – a) = 12 bits + 1sign bit●Dcontrol = 12 bits + sign bitSimulate what you build andBuild what you simulate ➲Million gate simulation of entire radio possibleLoop Filter➲α=5, ρ=0.5, Fref = 80MHz, λi=2^(-3), 2^(-4)∏1sFref1si∗FrefPhase Margin vs. Roll-off Trade-offs1 us Acquisition TimeTime (secs)Step ResponseQuantization Noise atTime to Digital Converter➲TDC=2*round((DivTime-RefTime)/100e-12 - 1Digital Oscillator Output0,2 and 4 pole Filter➲No pole is largest bandwidthQuantization Noise 500 Khz Quantization Noise with no FilteringLook Ahead Transformwith Loop Unrolling➲Cascade of single pole IIR filters➲y1(k) = (1-a1) * y1(k-1) + a1 * x(k)➲Substitution to transform loop●Look ahead to decrease iteration bound➲y1(k) = (1-a1)^2 * y1(k-2) + a1 * (1-a1) * x (k-1) + a1 * x(k)➲Loop unrolling ●Serial to parallel conversion➲y1(k) = (1-a1)^2 * y1(k-2) + a1 * (1-a1) * x (k-1) + a1 * x(k)➲y1(k-1) = (1-a1)^2 * y1(k-3) + a1 * (1-a1) * x (k-2) + a1 * x(k-1)➲➲Cascade of single pole filters➲y2(k) = (1-a1) * y2(k-1) + a1 * y1(k)Look Ahead Response➲Higher sampling frequency of 160 MHz used with look ahead to demonstrate speed-upConclusion➲Digital PLLs remove restriction of low band-width on loop filter➲Look ahead transformation can be used to arbitrarily speed up filter to achieve any design bandwidth➲Speed up achieved by loop unrolling and ex-tra hardware in terms of
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