Name ENGR160 Date Homework 9 Problem A 10 pts Design a clocked synchronous state machine that loops through the following states 1 3 5 7 Make sure that at reset the machine start in the state 1 by using FF with asynchronous CLR and SET 1 Draw the state diagram of the state machine What is the minimum number of FF required 2 Draw the gate level schematic of the state machine Problem B 30 pts Design a clocked synchronous state machine that loops through the following states 0 1 2 3 4 5 6 7 Assume that the only cells available are D flip flops and 2 input NAND gates The timing behavior of the NAND gates and the D flip flops are given in Table 1 Make sure that at reset the machine start in the state 0 by using D FF with asynchronous CLR 1 Draw the gate level schematic of the state machine 2 Find out what is the max frequency min clock period for which you can use the state machine you designed 1 Assume a clock cycle of T 40 ns and check if setup and hold time constraints are respected Hint make sure to use the proper delays Table 1 Min Delay ns Max Delay ns NAND tpd A or B to Z 1 5 8 0 2 5 10 D FF tpd CLK to Q 1 0 4 tsu D to CLK 0 5 2 th D from CLK A B Z D Q CLK CLR Page 1 of 2 Name ENGR160 Date OPTIONAL Problem 8 20 OPTIONAL Problem 8 83 OPTIONAL Problem 8 84 See Table 8 43 p 774 Page 2 of 2