CMSC 611: AdvancedCMSC 611: AdvancedComputer ArchitectureComputer ArchitectureInstruction Set Architecture (2)Instruction Set Architecture (2)Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slidesSome material adapted from Hennessy & Patterson / © 2003 Elsevier ScienceData is based on SPEC2000 on AlphaControl Flow InstructionsControl Flow Instructions• Jump: unconditional change in the control flow• Branch: conditional change in the control flow• Procedure calls and returnsDestination Address DefinitionDestination Address Definition• PC-relative addressing– Good for short position-independent forward &backward jumps• Register indirect addressing– Good for dynamic libraries, virtual functions &packed case statementsData is based SPEC2000 on AlphaName How condition is tested Advantages Disadvantages Condition Code (CC) Special bits are set by ALU operations, possibly under program control Sometimes condition is set for free CC is extra state. Condition codes constrain instructions’ ordering since they pass info. from one instruction to a branch Condition register Test arbitrary register with the result of a comparison Simple Uses up a register Compare & branch Compare is part of the branch. One instruction rather than two for a branch May be too much work per instruction Remember to focuson the common caseBased on SPEC92 on MIPSCondition EvaluationCondition EvaluationData is based on SPEC2000 on AlphaDifferent benchmark andmachine set new design priority DSPs support repeat instruction for for loops (vectors) using 3 registersFrequency of Types ofFrequency of Types ofComparisonComparisonType and Size of OperandsType and Size of Operands• Operand type encoded in instruction opcode– The type of an operand effectively gives its size• Common types include character, half word and wordsize integer, single- and double-precision floating point– Characters are almost always in ASCII, though 16-bitUnicode (for international characters) is gaining popularity– Integers in 2’s complement– Floating point in IEEE 754Unusual TypesUnusual Types• Business Applications– Binary Coded Decimal(BCD)• Exactly represents alldecimal fractions (binarydoesn’t!)• DSP– Fixed point• Good for limited rangenumbers: more mantissa bits– Block floating point• Single shared exponent formultiple numbers• Graphics– 4-element vector operations(RGBA or XYZW)• 8-bit, 16-bit or single-precision floating point8-bit exponent8-bit exponent24-bit mantissa24-bit mantissafixed exponentfixed exponent32-bit mantissa32-bit mantissaSize of OperandsSize of Operands• Double-word: double-precision floating point + addresses in 64-bit machines• Words: most integer operations + addresses in 32-bit machines• For the mix in SPEC, word and double-word data typesdominatesFrequency of reference by size based on SPEC2000 on AlphaExample: Assembly: ADD $t0, $s1, $s2 M/C language (binary): 000000 00001 00010 00000 00000 1000000000 0000 0010 0010 0000 0000 0010 0000 M/C language (hex): 0x00220020Note: MIPS compiler by default maps $s0,…,$s7 to reg. 16-23 and $t0,…,$t7 to reg. 8-15Instruction RepresentationInstruction Representation• All data in computer systems is represented in binary• Instructions are no exception• The program that translates the human-readable codeto numeric form is called an Assembler• Hence machine-language or assembly-languageEncoding an Instruction SetEncoding an Instruction Set• Affects the size of the compiled program• Also complexity of the CPU implementation• Operation in one field called opcode• Addressing mode in opcode or separate field• Must balance:– Desire to support as many registers and addressing modesas possible– Effect of operand specification on the size of the instruction(and program)– Desire to simplify instruction fetching and decoding duringexecution• Fixed size instruction encoding simplifies CPU designbut limits addressing choicesEncoding ExamplesEncoding ExamplesMIPS Instruction FormatsMIPS Instruction Formatsopcodes 000001010011100101110111000R-type jjalbeqbneblezbgtz001addiaddiusltisltiuandiorixori 010 011llolhitrap 100lblh lwlbulhu 101sbsh sw 110 111 funct codes 000001010011100101110111000sll srlsrasllv srlvsrav001jrjalr 010mfhimthimflomtlo 011multmultudivdivu 100addaddusubsubuandorxornor101 sltsltu 110 111The Stored Program ConceptThe Stored Program Concept• Today’s computers are builton two key principles :– Instructions are representedas numbers– Programs can be stored inmemory to be read orwritten just like numbers• Memory can contain:– the source code for an editor– the compiled m/c code forthe editor– the text that the compiledprogram is using– the compiler that generatedthe codeProcessorAccounting program(machine code)Editor program(machine code)C compiler(machine code)Payroll dataBook textSource code in Cfor editor programMemoryGPU Shading ISAGPU Shading ISA• Data– IEEE-like floating point– 4-element vectors• Most instructions perform operation on all four• Addressing– No addresses– ATTRIB, PARAM, TEMP, OUTPUT– Limited arrays– Element selection (read & write)• C.xyw, C.rgbaGPU Shading ISAGPU Shading ISA• Instructions:Instruction Operation Instruction Operation ABS r,s r = abs(s) MIN r,s1,s2 r = min(s1,s2) ADD r,s1,s2 r = s1+s2 MOV r,s1 r = s1 CMP r,c,s1,s2 r = c<0 ? s1 : s2 MUL r,s1,s2 r = s1*s2 COS r,s r = cos(s) POW r,s1,s2 r ! s1s2 DP3 r,s1,s2 r = s1.xyz • s2.xyz RCP r,s1 r = 1/s1 DP4 r,s1,s2 r = s1 • s2 RSQ r,s1 r = 1/sqrt(s1) DPH r,s1,s2 r = s1.xyz1 • s2 SCS r,s1 r = (cos(s),sin(s),?,?) DST r,s1,s2 r = (1,s1.y*s2.y,s1.z,s2.w) SGE r,s1,s2 r = s1"s2 ? 1 : 0 EX2 r,s r ! 2s SIN r,s r = sin(s) FLR r,s r = floor(s) SLT r,s1,s2 r = s1<s2 ? 1 : 0 FRC r,s r = s - floor(s) SUB r,s1,s2 r = s1-s2 KIL s if (s<0) discard SWZ r,s,cx,cy,cz,cw r = swizzle(s) LG2 r,s r ! log2(s) TEX r,s,name,nD r = texture(s) LIT r,s r = lighting computation TXB r,s,name,nD r = textureLOD(s) LRP r,t,s1,s2 r = t*s1 + (1-t)*s2 TXP r,s,name,nD r = texture(s/s.w) MAD r,s1,s2,s3 r = s1*s2 + s3 XPD r,s1,s2 r = s1 s2 MAX r,s1,s2 r = max(s1,s2)GPU Shading ISAGPU Shading ISA• Notable:– Many special-purpose instructions– No binary encoding, interface is text form• No ISA limits on future expansion• No ISA limits on registers• No ISA limits