Physics 623FPGA II: Construction of a ROMAug. 5, 20081 ObjectiveA 32 word 12 bit read-only memory (ROM) is constructed in the Spartan II FPGA and is used todrive three seven-segment displays with a programmed pattern. The ROM is constructed usingthe Xilinx CORE generator and the CORE memory editor. The ROM addresses are set by a fivebit binary counter which is driven with the test board external 100 MHz clock oscillator. Theclock frequency must be stepped down to make the display visible using, for example, the MSBof a 25 bit binary counter. We will program the ROM with the first 32 prime numbers, i.e. 2through 131 and read it out with the seven-segment displays.2 Procedure OutlineThe top level source will again be a schematic diagram. Since 32 prime numbers takes you into thehundreds, we have to use all three seven-segment displays and three seven-segment decoders. Wewill also again use a count stepdown for the external 100 MHz clock. The 32x12 ROM requiresfive address lines so we will need a five bit counter to sequentially address the ROM. Whilethe ROM can be built directly with VHDL coding, we will use a Xilinx to ol called the COREgenerator which is used to build preconfigured logic functions. ISE 8.1 or higher is required tosupport the CORE generator. The required counters and seven segment display decoders will beconstructed in VHDL language (easily done after working through the WebPack tutorial) andonce circuit symbols are created, all components can be entered into the circuit schematic.2.1 Xilinx CoresThe CORE generator can be used to produce devices ranging in complexity from simple arith-metic operators and delay elements to complex building-blocks such as digital signal decoders,processing filters, multiplexers, transformers, FIFOs, and memories.3 Core ImplementationThe Core to be built is treated in the Project Navigator like another type of new source.The Cores are built using the CORE generator which can be run either inside or outside theProject navigator. To start the CORE generator from within Xilinx ISE select N ewSourceand IP (Coregen&ArchitecturalW izard). The next window will pres ent a choice of Core types.Choose Memories & StorageElements, then RAM S & ROM s, and then D istributed M emory v7.1to make a ROM. After executing F inish a DistributedMemory window will open up which isa tool to construct the memory. Choose ROM, specify the required Depth and Width, go toNext, and then execute Generate. A .xco file will be generated, but remember that the ROMat this point is empty. Now you will run the Memory Editor to load data into the ROM. Withthe .xco file highlighted, click on ManageCores. From the window that opens up, load your1CORE .cgp Proj ect File and under T ools select the MemoryEditor. Choose a memory blockname and again sp ec ify the depth and width but you will now also be able to edit the memorycontents. Select 2 for the Address Radix (since you will address the ROM in binary) and select16 for the Data Radix since you will write the memory contents in Hex. Each memory entry willcontain three Hex characters corresponding to 12 bits. For example, entering the prime 5 willbe entered as 005 and the prime 131 will be entered as 131. When the memory contents havebeen entered, save the memory definition and execute Generate under the File menu item. SelectMaking a .coefile. Exit the Memory Editor after saving all the files. You now have created amemory definition but the data is not yet in the ROM. Double click on the .xco file name and theDistributedM emory window will open up showing the parameters of the ROM. Click on Nexttwo times and load the memory defintion file created earlier. You can check the memory contentsby clicking on ShowCoefficients. The CORE generation procedure will also have made a ROMcircuit symbol which will be available from the schematic window.4 Creating the BitmapOpen the schematic window and wire up the circuit. All the parts are available from the Symbolswindow. Rename the Clock input to CLK. No buffer is required for the Clock input but an obufpart is required for each output. The obufs must be renamed to match the 7 bit wide branchby renaming them to obufname(6:0). See the writeup circuit diagram. Check the schematic byrunning checkschematic and save the file.The next step is to assign the circuit pins. Create a new constraint file (.ucf) by adding a newsource of the constraint type. Highlighting the file name will show a AssignP ackageP ins in theP rocesses window. Clicking on this will open the PACE pin assignment editor f rom which youenter the required pin assignments. Save the file. You will find the Pin Assigments in the tableat the end of this report.Now Synthesize, Translate, Map, Place and Route as before. If you are successful, click onGenerateP rogrammingF ile and a .bit file will be created. Remenber to use the JTAG clock withthe USB cable or the CCLK clock with the parallel port cable. The .bit file is than downloadedinto the FPGA with the XE SS GXSLOAD tool.5 Downloading the CircuitThe binary configuration bit file is now ready to be downloaded to the actual FPGA chip. Followthe following steps for downloading.1. Make sure the circuit boards are connected to a +9V plug-in power supply.2. Make sure the circuit board is connected to the appropriate PC port using either the parallelport or USB serial cable.3. You will then use one of several available GXSTOOLS depending on which function youare trying to implement.• GXSTEST: This utility lets the user test an XS Board for proper functioning.2• GXSLOAD: This utility lets the user download FPGA configuration files to theFPGA. Cho ose the appropriate download port (either the Parallel or USB0 port)depending on which download cable you are using.• GXSPORT: This utility lets the user send logic inouts to an XS Board by togglingthe data pins of the parallel port.• GXSSETCLK: This utility allows you to set an integer divisor for the on-board 100MHz clock.6 Questions1. The ROM will be made up out of the Spartan II Block RAM. Our chip has eight BlockRAM cells each of which is a fully synchronous dual-port 4096-bit RAM giving 32 Kbitsof total Block RAM. The rest of the circuit has registers that are made up out of the DFlip-Flops in the CLB. Estimate the number of CLBs required to implement the circuitand compare your estimate to the information in the Project Status Report.2. Determine the maximum clock frequency for the circuit (It better be above 50 MHz).