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UCSD CSE 231 - Compiler-Directed Instruction Cache Leakage Optimizations

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Utilize compiler based techniqueCompiler strategiesImpact of compiler optimizationSummaryCompiler-Directed instruction cache leakage optimizations Compiler-Directed instruction cache leakage optimizations Discussed by Raid AyoubLeakage power: - Leakage power is the power consumed due to subthreshold leakage current - Leakage power: 30% of L1 power and 70% of L2 power for 0.13u.- Reducing leakage power improves battery life and reliability- Leakage power will be increasingly significant.Handling leakage power at the circuit level:- Apply gated Vdd (state-destroying)- Put cache in drowsy mode (state-preserving)Challenges in managing leakage-control modes of cache:- Distill at run time the inactive instructions and place them in leakage mode- Potential for performance degradation: Putting active instructions in leakage mode- Hardware overhead: power and latencyPrevious approaches: Utilize architectural-level techniquesUtilize hardware monitoring to manage the leakage modes of the cacheLimitations: - Hardware complexity- Power savings could be moderate Utilize compiler based technique- Identify the last use of instructions and place them in leakage mode- Special instructions are used to place cache lines into leakage modesGoals:- Simplifies hardware support- Improve power savingsTwo compiler-based strategies are studied:- Conservative- OptimisticTwo leakage savings mechanisms are utilized- State destroying and state preserving modeCompiler strategiesTurn off instructions are applied at the loop level granularity Conservative strategy: - The lines for loop body-I can only be turned off when exiting loop III- Less effective when loop III encloses the majority of instructions in the codeOptimistic strategy: - The lines for loop body-I can be turned off every time exiting loop I (Assume loop II take long time)Code fragment that contains three loopsWhen to turn off a cacheWhen to turn off a cache line?line?when incur a large gap in cycleswhen incur a large gap in cyclesOptimistic Optimistic strategystrategywhen sure its content is deadwhen sure its content is deadConservative Conservative strategystrategy- Experimental results show that applying optimistic strategy with state preserving leakage control mechanism provides appreciable energy savings and energy-dealyImpact of compiler optimizationVarious standard loop optimizations are examined, loop distribution, fusion, tiling andunrolling. Experimental results show that loop distributions is the most beneficial optimizationfor energy savings. Summary--Proposed approach delivers competitive energy savings and energy-delay toProposed approach delivers competitive energy savings and energy-delay toother schemesother schemes--Applying loop optimizations improves energy savingsApplying loop optimizations improves energy savings--Hardware support is simpleHardware support is simple--Adding explicit turn-off instructions impose modifications in ISAAdding explicit turn-off instructions impose modifications in


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UCSD CSE 231 - Compiler-Directed Instruction Cache Leakage Optimizations

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